Speaker:
Dr. Greg Steffan
University of Toronto
Title:
Nice Threads! Where did you get them? On Optimistic Parallelism
Date:
Monday, February 2, 2009
Time:
4:00 pm - 5:00 pm
Location:
EIT 3142
Abstract:
The microprocessor technology road-map predicts a future with tens
to hundreds of processors per chip and beyond, but with limited
clock frequency improvements and potentially simpler individual
processors. Faced with the corresponding demise of sequential program
performance, the software industry is compelled to parallelize existing
software by introducing threads and synchronization to target these
multicore processors. The difficulty is that the vast majority of
programmers are trained only in sequential programming, and do not
understand the pitfalls and subtleties of threaded programming.
In this talk I will provide an overview of two potential solutions to
this problem that exploit "optimistic parallelism". The first approach,
inspired by database transactions, is called "transactional memory" (TM).
TM provides an easier, optimistic alternative to locks for critical
sections---allowing programmers to avoid deadlock and fine-tuning when
synchronizing code, and also allowing critical sections to execute in
parallel whenever they operate on independent data. TM can be supported
entirely in software (with significant overhead), or ideally accelerated
by hardware support. TM has become very popular in academia, with dozens
of research projects including several at Intel, IBM, and SUN labs, and
the first real hardware support recently announced by SUN. I will also
describe a second more-aggressive approach to optimistic parallelism
called "thread-level speculation" (TLS), where legacy programs are
automatically divided into threads that execute speculatively, exploiting
available dynamic parallelism. TLS has also proven popular in academic
and industrial research, but has yet to be directly implemented in
commercial hardware.
Biography:
Greg Steffan is an Associate Professor in the Department of Electrical and
Computer Engineering at the University of Toronto. His expertise is in
computer architecture and compilers, and his research currently targets
methods of exploiting parallelism in multicore processors and FPGAs.
Greg completed his doctorate at Carnegie Mellon University in 2003,
after undergraduate and Masters degrees at the University of Toronto in
1995 and 1997 respectively. He is a recipient of the Ontario Ministry
of Research and Innovation Early Researcher Award Award (2007), a Siebel
Scholar (2002), an IBM CAS Faculty Fellow, a senior member of the IEEE,
and a member of the ACM.
