Hello. I am a third year PhD candidate at the ECE department, University of Waterloo (UWaterloo). My advisor is Prof. Hiren Patel. I work in the general area of computer architecture with specific interests in real-time embedded systems architecture and high performance computer architecture.

I received my Masters in Applied Sciences (MASc) from UWaterloo in 2014. My MASc thesis was on accelerating SystemC simulations on multi-core CPUs and GPUs. I was an IBMer at the IBM Software Lab in Toronto working with the POWER optimization team from 2014-2015.

Publications & Thesis


  1. Hassan, Mohamed, Anirudh Kaushik, and Hiren Patel. “Predictable Cache Coherence for Multi-Core Real Time Systems.” In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 2017.


  1. Hassan, Mohamed, Anirudh M. Kaushik, and Hiren Patel. “Reverse-Engineering Embedded Memory Controllers through Latency-Based Analysis.” In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2015.


  1. Kaushik, Anirudh Mohan. “Accelerating Mixed-Abstraction SystemC Models on Multi-Core CPUs and GPUs.” MASc Thesis, 2014.


  1. Kaushik, Anirudh M., and Hiren Patel. “Systemc-Clang: An Open-Source Framework for Analyzing Mixed-Abstraction SystemC Models.” In Proceedings of IEEE Forum on Specification and Design Languages (FDL). IEEE, 2013.
  2. Bertacco, Valeria, Debapriya Chatterjee, Nicola Bombieri, Franco Fummi, Sara Vinco, A. M. Kaushik, and Hiren D. Patel. “On the Use of GP-GPUs for Accelerating Compute-Intensive EDA Applications.” In Proceedings of the Conference on Design, Automation and Test in Europe. DATE ’13. EDA Consortium, 2013.


  1. Nanjundappa, M., A. Kaushik, H. D. Patel, and S. K. Shukla. “Accelerating SystemC Simulations Using GPUs.” In IEEE International High Level Design Validation and Test Workshop (HLDVT), 2012.