[1] Christian Fobel, Gary Gréwal, and Andrew Morton. Hardware accelerated FPGA placement. Microelectronics Journal, 40(11):1667-1671, November 2009. [ bib ]
[2] Andrew Morton and Wayne M. Loucks. Kernel and application partitioning for EDF schedule feasibility. In IEEE Toronto International Conference - Science and Technology for Humanity: Symposium on Electronic Design Automation, pages 575-580, September 2009. [ bib ]
[3] Santheeban Kandasamy, Andrew Morton, and Wayne M. Loucks. Configuration scheduling using temporal locality and kernel correlation. In IEEE International Symposium on Parallel and Distributed Processing - Reconfigurable Architectures Workshop, pages 1-5, April 2008. [ bib ]
[4] Christian Fobel, Gary Gréwal, and Andrew Morton. Hardware accelerated FPGA placement. In IEEE International Midwest Symposium on Circuits & Systems / IEEE International Northeast Workshop on Circuits & Systems, pages 1134-1137, August 2007. [ bib ]
[5] Andrew Morton and Wayne M. Loucks. EDF feasibility and hardware accelerators. In Multidisciplinary International Scheduling Conference: Theory and Applications, pages 368-376, Paris, France, August 2007. [ bib ]
[6] Andrew Morton, Insop Song, and Jeffrey Liu. Hardware data structure for real-time scheduling and concurrency. In IEEE International Conference on Field Programmable Logic and Applications (FPL), pages 476-479, Amsterdam, Netherlands, August 2007. [ bib ]
[7] Christian Fobel, Gary Gréwal, and Andrew Morton. A hardware-accelerated search algorithm for FPGA placement. In IEEE Canadian Conference on Computer and Electrical Engineering, pages 647-650, April 2007. [ bib ]
[8] Andrew Morton and Wayne M. Loucks. EDF feasibility analysis of accelerated tasks. In IEEE Canadian Conference on Computer and Electrical Engineering, pages 1519-1522, April 2007. [ bib ]
[9] G. Gréwal, S. Coros, D. Banerji, and A. Morton. Assigning data to dual memory banks in DSPs with a genetic algorithm using a repair heuristic. Journal of Applied Intelligence, 26(1):53-67, February 2007. [ bib ]
[10] G. Gréwal, S. Coros, D. Banerji, A. Morton, and M. Ventresca. Optimized memory assignment for DSPs. In IEEE Congress on Evolutionary Computation, pages 64-72, Vancouver BC, July 2006. [ bib ]
[11] G. Gréwal, S. Coros, A. Morton, and D. Banerji. A genetic algorithm penalty-function approach to the assignment of data to dual-bank DSPs. In IEEE Workshop on Interaction between Compilers and Computer Architectures, pages 2-12, Austin Texas, February 2006. [ bib ]
[12] G. Gréwal, A. Morton, S. Coros, and D. Banerji. Comparing a genetic algorithm penalty function and repair heuristic in the DSP application domain. In Conference on Artificial Intelligence and Applications, pages 31-39, Innsbruck Austria, February 2006. [ bib ]
[13] G. Gréwal, S. Coros, A. Morton, and D. Banerji. A multi-objective integer-linear programming model for assigning data to memory in the DSP domain. SIGMICRO: ACM Special Interest Group on Micro-Architectural Research and Publishing, 24(1):1-10, 2006. [ bib ]
[14] Andrew Morton and Wayne M. Loucks. A hardware/software kernel for system on chip designs. In Proceedings of the ACM Symposium on Applied Computing, pages 869-875, 2004. [ bib ]
[15] Andrew Morton. Hardware/Software Partitioning and Scheduling of Embedded Systems. PhD thesis, University of Waterloo, 2004. [ bib ]
[16] G. Gréwal, T. Wilson, and A. Morton. An ega approach to the compile-time assignment of data to multiple memories in digital-signal processors. ACM SIGARCH Computer Architecture News, 31(1):49-59, March 2003. [ bib ]
[17] Andrew Morton and Wayne M. Loucks. Real-time kernel support for coprocessors: Empirical study of an SoPC. In Proceedings of the Embedded Systems and Applications Conference, pages 10-15, 2003. [ bib ]
[18] Andrew Morton. Automating embedded system design. Graduate Student Research Conference, University of Waterloo, 2001. Oral Presentation. [ bib ]
[19] Andrew Morton. Retargetable code generation for application specific processors. Master's thesis, University of Guelph, 1996. [ bib ]
[20] T. Wilson, G. Grewal, H. Pulley, A. Morton, A. Bialecki, A. Dasgupta, and D. Banerji. A retargetable code generator for DSP applications. Canadian Microelectronics Corporation Conference, 1996. Poster. [ bib ]

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