technology has made a remarkable progress during the last three decades. The number of transistors per chip has doubled every couple of years as predicted by the Moore's law. Aggressive technology scaling has enabled implementing complex systems-on-chip (SoCs), which integrate embedded memory, high-performance logic, signal processing circuits, and analog/mixed signal circuits on the same chip. However, as the transistor lengths are entering in the sub-100 nm regime, the design, manufacturing and testing of ICs is becoming extremely challenging due to increasing impact of several secondary effects which have been ignored in the past. These secondary effects include subthreshold leakage, hot-electron effects, oxide-tunneling, gate leakage, DIBL, GIDL, band-to-band tunneling, device parameter variations, reverse and normal short/narrow channel effects, source/drain series resistance, quantum effects on threshold voltage, velocity saturation and overshoot effects, gate resistance, interconnect parasitics, etc. A careful consideration of these effects is critical in design, manufacturing and testing phases of ICs to fully exploit the advantages of current CMOS technologies. It is thus important to consider issues like power and thermal management, noise tolerance, yield and long term reliability, interconnect scaling, and so on, early in the design phase. Furthermore, a designer has to pay special attention to physical design and issues like die-to-die and within-die process variations.

Our group is exploring many of these complex issues of modern CMOS ICs. Our research includes analog and mixed signal circuit design, embedded memory design, design for reliability and testability, and high-performance/low-power circuit design. Our research projects address some of the most pressing issues faced by the semiconductor industry today. We have access to industry standard CMOS technologies (180nm through 65nm), which enable us substantiating our ideas with silicon results.

For questions and comments, please contact Dr. Manoj Sachdev

Image Courtesy: Scanning electron microscope image showing the six-level copper interconnect technology used in IBM's CMOS 7S fabrication technology (copyright IBM Corporation)