Key Contributions


  1. Andrei Pavlov, and Manoj Sachdev, CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: - Process-Aware Design and Test, pp. 200, Springer, ISBN 978-14020-8363-4, 2007.
  2. Manoj Sachdev, and Jose Pineda, Defect Oriented Testing for Nano-metric CMOS VLSIs, 2nd Edition, pp. 350, Springer, ISBN 978-0-387-46546-3, 2006.


  1. Maofeng Yang, Nikolas P. Papadopoulos, William S. Wong, and Manoj Sachdev, Apparatus and Method for Electrical Stability Compensation, US patent 9,083,320, July 2015.
  2. David Rennie, M. Sachdev, SRAM Sense Amplifier, US patent 8,536,898, September 2013.
  3. M. Sachdev, M. Sharifkhani, David Rennie, Jaspal Shah, Sense-Amplification with Offset Cancellation for Static Random Access Memories, US Patent , 8,488,403, July 2013.
  4. M. Sachdev, D.J. Rennie, SRAM Cell Without Dedicated Access Transistors, US Patent 8,072,797, December 2011.
  5. M. Sachdev, S.M. Jahinuzzaman, Soft Error Robust Random Access Memory Cell Storage Configuration, US Patent, 7,872,938, January 2011.
  6. Manoj Sachdev, Separate IDDQ Testing of Signal Path and Bias Path in an IC, U.S. Patent, 5,625,300, April 1997.


  1. A. Neale, M. Sachdev, A 0.4 V 75 kbit SRAM macro in 28 nm CMOS featuring a 3-adjacent MBU Correcting ECC, IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, September 2014 (Best Poster Award).
  2. David Li, Pierce Chuang, David Rennie, David Nairn, Manoj Sachdev, Design and Analysis of Metastable-Hardened and Soft-Error Tolerant High-Performance, Low-Power Flip-Flops, IEEE International Symposium on Quality Electronics Design, March 2011 (Best Paper Award).
  3. S. M. Jahinuzzaman, D. Rennie, M. Sachdev, A Soft Error Tolerant 10T SRAM Bit-cell with Differential Read Capability, IEEE Transactions on Nuclear Science, Vol.56, No.6, Part 2, pp. 3768-73, December 2009.
  4. M. Elgebaly, and M. Sachdev, Variation-Aware Adaptive Voltage Scaling System, IEEE Transaction on VLSI Systems, vol. 15, Issue 5, pp. 560-571, May 2007.
  5. M. Maymandi-Nejad, and M. Sachdev, A Monotonic Digitally Controlled Delay Element, IEEE Journal of Solid State Circuits, IEEE Journal of Solid State Circuits, Volume 40, Issue 11, pp. 2212 - 2219, November 2005.
  6. M. Sachdev, P. Jansen, and V. Zieren, Defect Detection with Transient Current Testing and its Potential for Deep Sub-micron ICs, Proceedings of IEEE International Test Conference, pp. 204-213, October, 1998, Washington DC, USA (Honorable Mention Award).
  7. M. Sachdev, Deep Sub-micron IDDQ Testing: Issues and Solutions, Proceedings of IEEE European Design and Test Conference, pp. 271- 278, 1997, Paris, France (Best paper award).