Selected Patents

Granted

• M. Sachdev, M. Sharifkhani, "Segmented column virtual ground scheme in a static random access memory (SRAM) circuit," US Patent No. 7372721, Granted May 13, 2008.



• J. Pineda De Gyvez, M. Sachdev, A. Pavlov, "Test for weak SRAM cells," US Patent No. 7200057, Granted April 3, 2007.



• A. Keshavarzi, B. Chatterjee, R. Krishnamurthy, M. Sachdev, "Low frequency testing, leakage control, and burn-in control for high-performance digital circuits," US Patent No. 6765414, Granted July 20, 2004.



• S. Hsu, B. Chatterjee, R. Krishnamurthy, "Low clock swing latch for dual-supply voltage design," US Patent No. 6762957, Granted July 13, 2004.



• S. Hsu, B. Chatterjee, R. Krishnamurthy, "Level converting latch," US Patent No. 6563357, Granted May 13, 2003.



• M. Sachdev, "Iddq-testable uni-directional master-slave," US Patent No. 6445235, Granted September 3, 2002.



• J. Tschanz, M. Sachdev, S. Narendra, V. De, "Stack-based impulse flip-flop with stack node pre-charge and stack node pre-discharge," US Patent No. 6429711, Granted August 6, 2002.



• M. Sachdev, S. Narendra, "High performance impulse flip-flops," US Patent No. 6369631, Granted April 9, 2002.



• M. Sachdev, S. Narendra, "High performance impulse flip-flops," US Patent No. 6366147, Granted April 2, 2002.



• M. Sachdev, "Electronic device selectably operable as a sequential logic circuit or a combinatorial logic circuit and circuit testing method," US Patent No. 6134688, Granted October 17, 2000.



• M. Sachdev, "IDDQ testable programmable logic arrays," US Patent No. 6127838, Granted October 3, 2000.



• M. Sachdev, "Testing control signals in A/D converters," US Patent No. 5,969,653, Granted October 19, 1999.



• M. Sachdev, "Fault-tolerant memory address decoder," US Patent No. 5831986, Granted November 3, 1998.



• M. Sachdev, "MOS master-slave flip-flop with reduced number of pass gates," US Patent No. 5831463, Granted November 3, 1998.



• M. Sachdev, B. Atzema, "Method for testing an electronic circuit by logically combining clock signals, and an electronic circuit provided with facilities for such testing," US Patent No. 5781025, Granted July 14, 1998.



• M. Sachdev, B. Atzema, "I.sub.DDQ -testing of bias generator circuit," US Patent No. 5751141, Granted May 12, 1998.



• M. Sachdev, "Separate I.sub.DDQ -testing of signal path and bias path in an IC," US Patent No. 5625300, Granted April 29, 1997.



• M. Sachdev, "Memory testing through cumulative word line activation," US Patent No. 5495448, Granted February 27, 1996.



• M. Sachdev, "I.sub.DDQ -testable RAM," US Patent No. 5,491,665, Granted February 13, 1996.

Pending

• M. Sachdev, S. M. Jahinuzzaman, “Soft error robust flip-flop cells,” US Patent, filed March 29, 2008.



• M. Sachdev, S. M. Jahinuzzaman, “Soft error robust static random access memory cells,” US Patent Application No. 20080094925, filed October 22, 2007.



• M. Sachdev, M. Sharifkhani, "Asymmetric four-transistor SRAM cell," US Patent Application No. 20070177419, filed August 2, 2007.



• J. Pineda de Gyvez, M. Sachdev and A. Pavlov, "Method and Apparatus to Detect Weak SRAM cells" Pending.

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