Research
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Analog and Mixed Signal Circuits
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Embedded Memories
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Digital Circuits
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VLSI Reliability and Testability
]
Thrust Areas:
- ESD protection circuits for high speed, mixed signal I/Os and RF circuits
- Soft error tolerant design of scaled-down logic circuits and flip-flops
- Impact of technology scaling on reliability/quality and testing of ICs
- Thermal management
- Optimization of current/logic and burn-in testing for high-leakage CMOS technologies
- Yield loss and thermal run away issues of burn-in testing
- Device physics and circuit design for reliability
- IDDX testing
Accomplishments:
- Designed and taped-out a chip which contains a novel methodology for testing high-performance pipelined circuits with slow-speed testers
- The chip also contains a clock timing circuit capable of achieving a timing resolution of 50ps
- Analysed the impact of technology scaling on bridging fault modeling and detection in CMOS circuits
- Analysed the impact of technology scaling on thermal management during burn-in
- Designed and analyzed novel ESD protection circuits for high-speed, mixed signal I/Os and RF circuits
- Simulated the above techniques and circuits using device simulators such as Medici