| Prof. Mohamed I. Elmasry |
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| Citations (Partial List): 1. M. Alioto and G. Palumbo "Highly Accurate and Simple Models for CML and ECL Gates", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 18, No.9, September 1999, pp.1369-1375.a. Citation of K. M. Sharaf and M.I. Elmasry, "An Accurate Analytical Propagation Delay Model for High-Speed CML bipolar circuits", IEEE J. Solid-State Circuits, vol.29, pp.31-45, Jan. 1994. 2. J.M.Casalta et al "Substrate Coupling", JSSC, April 1997, pp.598-603.
3. The work on Novel High Speed Circuit Structures for BiCMOS Environment (R.X. Gu and M.I. Elmasry, IEEE Journal of Solid-State Circuits, May 1995, pp.563- 570) has been referred to by:a. Y.K. Seng, S.S. Rofail, "1.5V High-Speed Low Power CMOS Current Sense Amplifier", Electronics Letters, Nov 1995, Vol. 31, No. 23, pp.1991-1993. 4. The work on Pipelined Architecture for Neural-Network-Based Speech Recognition (D. Zhang, L. Deng and M.I. Elmasry, Int. Journal of Neural, Parallel and Scientific Computations, Vol. 2, No. 1, 1994, pp.81-92) has been referred to by:a. D. Zhang, M.I. Elmasry, "A Digital Perceptron Learning Implementation with Look-Up Table Feedback Layer", Journal of Circuits, Systems and Computers, Feb 1996, Vol. 6, No. 1, pp.79-84. 5. The work on An Accurate Analytical Propagation Delay Model (K.M. Sharaf and M.I. Elmasry, IEEE Journal of Solid State Circuits, January 1994, Vol. 29, No. 1, pp.31-45) has been referred to by:a. K.M. Sharaf and M.I. Elmasry, "Analysis and Optimization of Series-Gated CML and ECL High Speed Bipolar Circuits", IEEE Journal of Solid State Circuits, Feb 1996, Vol. 31, No. 2, pp.202-211) 6. The work on Novel Low-Voltage Low-Power Full-Swing BiCMOS Circuits (M.S. Elrabaa, M.S. Obrecht and M.I. Elmasry, IEEE Journal of Solid-State Circuits, Feb 1994, Vol. 29, No. 2, pp.86-93) has been referred to by:a. P. Routley, A. Brunnschweiler, P. Ashburn, "Optimization of BiCMOS Buffers For Low-Voltage Applications", Electronics Letters, June 1994,Vol. 30, No. 13, pp.1046-1048.
7. a. R.X. Gu, M.I. Elmasry, "All-N-Logic High-Speed True-Single-Phase Dynamic CMOS Logic", IEEE Journal of Solid State Circuits, Feb 1996, Vol. 31, No. 2, pp.221-229. 8. The work on Speeding-Up of Convergence of Gummel Iterations for Transient Simulation (M.S. Obrecht, M.I. Elmasry, Int. Conference NASECODE IX, Copper Mountain, Colorado, Dec 1993, published in COMPEL - Int. Journal for Computation and Math in E&E, James and James Science Publishers, 1994, Vol. 12, No. 4, pp.311-317) has been referred to by:a. M.S. Obrecht, M.I. Elmasry, E.L. Heasell, "TRASIM - Compact and Efficient 2-Dimensional Transient Simulator for Arbitrary Planar Semiconductor-Devices", IEEE Transactions on CAD of Integrated Circuits and Systems, April 1995, Vol. 14, No. 4, pp.447-458. 9. The work on Full Swing Schottky BiCMOS/BiNMOS (A. Bellaouar, I.S. Abu-Khater, M.I. Elmasry and A. Chikima, IEEE Journal of Solid-State Circuits, June 1994, Vol 29, pp.693-700) has been referred to by:a. S.M. Rezaul Hassan and C.D. Rajagopal, "Low-Voltage Dynamic BiCMOS CLA Circuit With Carry Skip Using Novel Full-Swing", IEEE JSSC, January 1997, pp70-78. b. A. Bellaouar, M.I. Elmasry, S.H.K. Embabi, "Bootstrapped Full-Swing BiCMOS/BiNMOS Logic-Circuits For 1.2-3.3 V Supply Voltage Regime", IEEE Journal of Solid-State Circuits, 1995, Vol. 30, No. 6, pp.629-636. c. S.C. Ma, E.J. McCluskey, "Open Faults in BiCMOS Gates", IEEE Transactions on Computer-Aided Design Of Integrated Circuits and Systems, May 1995, Vol. 14, No. 5, pp.567-575. 10. The work on Further Improvements in Decoupled Methods for Semiconductor Device Modeling (M.S. Obrecht, K.C. Wu, R.W. Dutton, E.L. Heasell, M.I. Elmasry, Proc. of the International workshop on Numerical Modeling of Processes and Devices for Integrated Circuits: NUPAD V, Honolulu, Hawaii, June 1994, pp.129-132) has been referred to by:a. M.S. Obrecht, M.I. Elmasry, E.L. Heasell, "Comparison of Coupled and Decoupled Methods for Semiconductor-Device Modeling", COMPEL - The International Journal for Computation and Mathematics in Electrical and Electronic Engineering, Dec 1994, Vol. 13, No. 4, pp.785-794. b. M.S. Obrecht, M.I. Elmasry, E.L. Heasell, "TRASIM - Compact and Efficient 2-Dimensional Transient Simulator for Arbitrary Planar Semiconductor-Devices", IEEE Transactions on CAD of Integrated Circuits and Systems, April 1995, Vol. 14, No. 4, pp.447-458. 11. The work on A New Model for BiCMOS Bipolar Transistors at High Current (R.X.W. Gu, M.I. Elmasry, D.J. Roulston, IEEE Journal of Solid State Circuits, Feb 1993, Vol. 28, No. 2, pp.173-175) has been referred to by:a. S.Y. Zhang, T.S. Kalkur, S. Lee, D.Y. Chen, "Analysis of the Switching Speed of BiCMOS Buffer under High Current", IEEE Journal of Solid State Circuits, July 1994, Vol. 29, No. 7, pp.787-796. 12. The work on VLSI Implementation of a Prototype MLP Using Novel Programmable Switched-Resistor CMOS ANN Chip (R.E. Rehan, M.I. Elmasry, Proc. of World Congress on Neural Networks Conference, (WCNN 93 Portland), Portland, Oregon, July 1993, pp.95-98) has been referred to by:a. J.G. Elias, D.P.M. Northmore, "Switched Capacitor Neuromorphs with Wide-Range Variable Dynamics", IEEE Transactions on Neural Networks, Nov 1995, Vol. 6, No. 6, pp.1542-1548. 13. The work on Determination of Limits on Non-Idealities for Analog Neural Network Hardware (A. Achyuthan, M.I. Elmasry, Proc. of World Congress on Neural Networks Conference, (WCNN 93 Portland), Portland, Oregon, July 1993, pp.839-843) has been referred to by:a. A. Achyuthan, M.I. Elmasry, "Mixed Analog-Digital Hardware Synthesis of Artificial Neural Networks", IEEE Transactions on CAD of Integrated Circuits and Systems, Sep 1994, Vol. 13, No. 9, pp.1073-1087. 14. The work on Global Optimization Approach for Architectural Synthesis (C.H. Gebotys, M.I. Elmasry, IEEE Transactions on CAD of Integrated Circuits and Systems, Sep 1993, Vol. 12, No. 9, pp.1266-1278) has been referred to by:a. D.L. Springer, D.E. Thomas, "Exploiting the Special Structure of Conflict and Compatibility Graphs in High-Level Synthesis", IEEE Transactions on CAD of Integrated Circuits and Systems, July 1994, Vol. 13, No. 7, pp.843-856. b. W.F.J. Verhaegh, P.E.R. Lippens, E.H.L. Aarts, J.H.M. Korst, J.L. Vanmeerbergen, A. Vanderwerf, "Improved Force-Directed Scheduling in High- Throughput Digital Signal-Processing", IEEE Transactions on CAD of Integrated Circuits and Systems, Aug 1995, Vol. 14, No. 8, pp.945-960. 15. The work on BiCMOS at Low Supply Voltage (M.I. Elmasry, A. Bellaouar, Proc. of the Bipolar Circuits and Technology Meeting (BCTM 93), [Invited Paper], Minneapolis, MN., Oct 1993, pp.89-96) has been referred to by:a. A. Bellaouar, I.S. Abukhater, M.I. Elmasry, A. Chikima, "Full-Swing Schottky BiCMOS BiNMOS and the Effects of Operating Frequency and Supply Voltage Scaling", IEEE Journal of Solid State Circuits, June 1994, Vol. 29, No. 6, pp.693-700. b. J.D. Warnock, "Silicon Bipolar Device Structures for Digital Applications - Technology Trends and Future-Directions", IEEE Transactions on Electron Devices, March 1995, Vol. 42, No. 3, pp.377-389. c. A. Bellaouar, M.I. Elmasry, S.H.K. Embabi, "Bootstrapped Full-Swing BiCMOS/ BiNMOS Logic-Circuits For 1.2-3.3 V Supply Voltage Regime", IEEE Journal of Solid-State Circuits, 1995, Vol. 30, No. 6, pp.629-636. 16. The work on Design for Testability of BiCMOS Logic Circuits (M.Y. Osman , M.I. Elmasry, Proc. of the International Conference on Microelectronics, (ICM 93), Dhahran, Saudi Arabia, Dec 1993, pp.172-175) has been referred to by:a. S. Hessabi, M.Y. Osman, M.I. Elmasry, "Differential BiCMOS Logic-Circuits - Fault Characterization and Design-for-Testability", IEEE Transactions on VLSI Systems, Sep 1995, Vol. 3, No. 3, pp.437-445. 17. The work on Analysis of Latchup and Parasitic effects in Merged BiCMOS Structures (S.S. Rofail, M.I. Elmasry, IEEE Journal of Solid State Circuits, Dec. 1993, Vol. 28, No. 12, pp.1389-1394) has been referred to by:a. S.S. Rofail, Y.K. Seng, "Novel Low-Voltage BiCMOS Digital Circuits Employing A Lateral P-N-P BJT in a P-MOS Structure", IEE Proceedings-Circuits Devices and Systems, April 1996, Vol. 143, No. 2, pp.83-90. b. S.S. Rofail, M.I. Elmasry, "Schottky Merged BiCMOS Structures", IEEE Journal of Solid State Circuits, March 1994, Vol. 29, No. 3, pp.356-361. 18. The work on Analysis and Design of BiCMOS Integrated Circuits", (M.I. Elmasry, Editor, IEEE Press, 1993) has been referred to by:a. A.E. Salama, M.I. Elmasry, "Fault Characterization, Testing Considerations, and Design for Testability of BiCMOS Logic Circuits", IEEE Journal of Solid State Circuits, Vol. 27, No. 6, June 1992, pp. 944-947. 19. The work on The Digi-Neocognitron,, (B.A. White and M.I. Elmasry, IEEE Transactions on Neural Networks, Vol. 3, No. 1, January 1992, pp.73-85), has been referred to by:a. D. Zhang, M.I. Elmasry, "A Digital Perception Learning Implementation with Look-Up Table", Journal of Circuits, Systems and Computers, Feb. 1996, Vol. 6, No. 1, pp. 79-84. b. C.N. Zhang, M. Wang, C.C. Tseng, "Residue Systolic Implementations for Neural Networks", Neural Computing & Applications, 1995, Vol. 3, No. 3, pp.149-156. c. T. Shibata, H. Kosaka, H. Ishii, T. Ohmi, "A Neuron-MOS Neural Network Using Self-Learning-Compatible Synapse Circuits", IEEE Journal of Solid-State Circuits, August 1995, Vol. 30, No. 8, pp.913-922. d. H. Card, "Digital VLSI Back Propagation Networks", Canadian Journal of Electrical and Computer Engineering, Jan. 1995, Vol. 20, No. 1, pp.15-23. e. A.P. Pathak, D.K.D. Majumder, "Approaches to Supervised Learning for Pattern-Recognition", Indian Journal of Pure and Applied Mathematics, Jan-Feb 1994, Vol. 25, No. 1-2, pp.1-38. f. M. Marchesi, G. Orlandi, F. Piazza, A. Uncini, "Fast Neural Networks without Multipliers", IEEE Transactions on Neural Networks, Vol. 4, No. 1, January 1993, pp. 53-62. 20. The work on Optimal Synthesis of High Performance Architectures, (C.H. Gebotys and M.I. Elmasry, IEEE Journal of Solid-State Circuits, March 1992, Vol. 27, No. 3, pp.389-397) has been referred to by:a. C.Y. Wang, K.K. Parhi, "Resource-Constrained Loop List Scheduler for DSP Algorithms", Journal of VLSI Signal Processing, Oct-Nov 1995, Vol. 11, No. 1-2, pp.75-96. b. M. Rim, Y. Fanny, R. Jann, "Global Scheduling with Code-Motions for High-Level Synthesis Applications", IEEE Transactions on VLSI Systems, September 1995, Vol. 3, No. 3, pp.379-392. c. M.K. Dhodhi, F.H. Hielscher, R.H. Storer, "Datapath Synthesis Using a problem-Space Genetic Algorithm", IEEE Transactions on Computer- Aided Design Of Integrated Circuits and Systems, August 1995, Vol. 14, No. 8, pp.934-944. d. C.Y. Wang, K.K. Parhi, "High Level DSP Synthesis Using Concurrent Transformations, Scheduling and Allocation", IEEE Transactions on Computer-Aided Design Of Integrated Circuits and Systems, March 1995, Vol. 14, No. 3, pp.274-295. e. K.K. Parhi, "High Level Algorithm and Architecture Transformation for DSP Synthesis", Journal of VLSI Signal Processing, Jan. 1995, Vol. 9, No. 1-2, pp.121-143. f. M.J. Rim, R. Jain, "Lower-Bound Performance Estimation for the High Level Synthesis Scheduling Problem", IEEE Transactions on Computer- Aided Design Of Integrated Circuits and Systems, April 1994, Vol. 13, No. 4, pp.451-458. g. A. Achyuthan, M.I. Elmasry, "Mixed Analog-Digital Hardware Synthesis of Artificial Neural Networks", IEEE Transactions on Computer-Aided Design Of Integrated Circuits and Systems, Sep. 1994, Vol. 13, No. 9, pp.1073-1087. h. I. Ahmad, M.K. Dhodhi, K. Saleh, R.H. Storer, "High-Level Synthesis of Self-Recoverable Asics Using Micro Rollback", International Journal of Electronics, Nov. 1993, Vol. 75, No. 5, pp.919-932. i. I. Ahmad, C.Y.R. Chen, "Datapath Synthesis Using Onchip Multiport Memories", IEE Proceedings-E Computers and Digital Techniques, July 1993 , Vol. 140, No. 4, pp.227-232. j. C.H. Gebotys, "Synthesizing Embedded Speed-Optimized Architectures", IEEE Journal of Solid-State Circuits, March 1993, Vol. 28, No. 3, pp.242- 252. 21. The work on Low Voltage Scaled CMOS and BiCMOS Digital Circuits (A. Bellaouar, M.I. Elmasry, IEEE Transactions on Electron Devices, April 1992, Vol. 39, No. 4, pp.1005-1009) has been referred to by:a. Y.K. Seng, S.S. Rofail, "Full-Swing High-Speed CBICMOS Digital Circuit for Low-Voltage Applications", IEE Proceedings-Circuits Devices and Systems, Feb 1995, Vol. 142, No. 1, pp.8-14. 22. The work on Analytical and Numerical Analyses of Delay Time of BiCMOS Structures (S.S. Rofail and M.I. Elmasry, IEEE Journal of Solid State Circuits, May 1992, Vol. 27, No. 5, pp.834-839) has been referred to by:a. S.S. Rofail, M.I. Elmasry, "Temperature-Dependent Characteristics of BiCMOS Digital Circuits", IEEE Journal of Solid State Circuits, Jan 1993, Vol. 40, No. 1, pp.169-178. b. S.S. Rofail, "Low-Voltage, Low-Power BiCMOS Digital Circuits", IEEE Journal of Solid State Circuits, May 1994, Vol. 29, No. 5, pp.572-579. c. S.Y. Zhang, T.S. Kalkur, S. Lee, D.Y. Chen, "Analysis of the Switching Speed of BiCMOS Buffer under High-current", IEEE Journal of Solid State Circuits, July 1994, Vol. 29, No. 7, pp.787-796. d. S.Y. Zhang, T.S. Kalkur, "Analysis of BiCMOS Buffer For Input Voltages with Finite Rise-Time", IEEE Journal of Solid State Circuits, July 1994, Vol. 29, No. 7, pp.797-807. 23. The work on Design and Optimization of Buffer Chains and Logic Circuits (M. Elrabaa and M.I. Elmasry, IEEE Journal of Solid State Circuits, May 1992, Vol. 27, No. 5, pp.792-801) has been referred to by:a. M.S. Elrabaa, M.S. Obrecht, M.I. Elmasry, Novel Low-Voltage Low- Power Full-Swing BiCMOS Circuits, IEEE Journal of Solid-State Circuits, Feb 1994, Vol. 29, No. 2, pp.86-94. b. S.S. Rofail, Y.K. Seng, "1.1V Full-Swing Double Bootstrapped BiCMOS Logic Gates", IEE Proceedings-Circuits Devices and Systems, Feb 1996, Vol. 143, No. 1, pp.41-45. c. S.S. Rofail, Y.K. Seng, "Novel Low-Voltage BiCMOS Digital Circuits Employing A Lateral P-N-P BJT in a P-MOS Structure", IEE Proceedings-Circuits Devices and Systems, April 1996, Vol. 143, No. 2, pp.83-90. d. S.S. Rofail, Y.K. Seng, "New Complementary BiCMOS Digital Gates For Low-Voltage Environments", Solid-State Electronics, May 1996, Vol. 39, No. 5, pp.681-687. 24. The work on Fault Characterization, Testing Considerations and Design for Testability of BiCMOS Logic Circuits (A.E. Salama, M.I. Elmasry, IEEE Journal of Solid State Circuits, June 1992, Vol. 27, No. 6, pp.944-947) has been referred to by:a. S. Hessabi, M.Y. Osman, M.I. Elmasry, "Differential BiCMOS Logic-Circuits-Fault Characterization and Design-for-Testability", IEEE Transactions on VLSI Systems, September 1995, Vol. 3, No. 3, pp.437-445. b. S.C. MA, E.J. McCluskey, "Open Faults in BiCMOS Gates", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, May 1995, Vol. 14, No. 5, pp.567-575. c. Z.H. You, E. Sanchezvincencio, J.P. Degyvez, "Analog System-Level Fault-Diagnosis Based on a Symbolic Method in the Frequency-Domain", IEEE Transactions on Instrumentation and Measurement, Feb 1995, Vol. 44, No. 1, pp.28-35. 25. The work on STAIC: An Interactive Framework for Synthesizing CMOS and BiCMOS Analog Circuits (J.P. Harvey, M.I. Elmasry and B. Leung, IEEE Transactions on CAD, November 1992, Vol. 11, No. 11, pp.1402-1417) has been referred to by:a. E.S. Ochotta, R.A. Rutenbar, L.R. Carley, "Synthesis of High-performance Analog Circuits in ASTRX/OBLX", IEEE Transactions on Computer- Aided Design Of Integrated Circuits and Systems, March 1996, Vol. 15, No. 3, pp.273-294. 26. The work on Towards Connectionist Production Systems (A.S. Bhogal, R.E. Seviora and M.I. Elmasry, Expert Systems with Applications, 1991, Vol. 2, No. 1, pp.3-14) has been referred to by:a. L. Medsker, E. Turban, "Integrating Expert-Systems and Neural Computing for Decision Support", Expert Systems with Applications, Oct-Dec 1994, Vol. 7, No. 4, pp.553-562. b. C. Loukatzikos, J.E. Galletly, "Constructing Neural Networks from Expert-System Rules", Journal of Microcomputer Applications, Jan 1994, Vol. 17, No. 1, pp.35-53. 27. The work on New Full Voltage Swing BiCMOS Buffers, (S.H.K. Embabi, A. Bellaouar, M.I. Elmasry and R.A. Hadaway), IEEE Journal of Solid State Circuits, Vol. 26, No. 2, February 1991, pp.150-153) has been referred to by:a. T.C. Lu and J.B. Kuo, "An Analytical Pull-Up Transient Model for a BiCMOS Inverter", Solid-State Electronics, Vol. 35, No. 1, January 1992, pp.1-8. b. A. Bellaouar, S.H.K. Embabi and M.I. Elmasry, "Low-Voltage Scaled CMOS and BiCMOS Digital Circuits", IEEE Transactions on Electron Devices, Vol. 39, No. 4, April 1992, pp. 1005-1009. c. H.S. Cho and J.G. Fossum, "Polysilicon Emitter Design for Scaled BiCMOS Circuits", Solid-State Electronics, Vol. 35, No. 9, September 1992, pp.1277-1284. d. M. Hiraki, K. Yano, M. Minami, K. Sato, N. Matsuzaki, A. Watanabe, T. Nishida, K. Sasaki, K. Seki, "A 1.5-V Full-Swing BiCMOS Logic Circuit", IEEE Journal of Solid-State Circuits, Vol. 27, No. 11, November 1992, pp.1568-1574. e. S.Y. Zhang, T.S. Kalkur, S. Lee, L. Gatza, "A Delay Model and Optimization Method of a Low-Power BiCMOS Logic-Circuit", IEEE Journal of Solid State Circuits, Oct 1994, Vol. 29, No. 10, pp.1191-1199. f. A. Bellaouar, I.S. Abukhater, M.I. Elmasry, A. Chikima, "Full-Swing Schottky BiCMOS BiNMOS and the Effects of Operating Frequency and Supply Voltage Scaling", IEEE Journal of Solid State Circuits, June 1994, Vol. 29, No. 6, pp.693-700. g. M. Elhady, M.H. Elsaid, I.M. Hafez, H. Haddara, "New Full-Voltage-Swing Multi-Drain Multi-Collector Complementary BiCMOS Buffers (M(2)CBiCMOS)", Solid-State Electronics, Jan 1995, Vol. 38, No. 1, pp.211-216. h. P. Mattei, S. Graffi, Z.M. Kovacsv, G. Masetti, "Design of Integrated BiCMOS Operational-Amplifiers with Low-Probability EMI-Induced-Failures", Microelectronics and Reliability, March 1995, Vol. 35, No. 3, pp.567-586. i. A. Bellaouar, M.I. Elmasry, S.H.K. Embabi, "Bootstrapped Full-Swing BiCMOS/BiNMOS Logic-Circuits for 1.2-3.3 V Supply Voltage Regime", IEEE Journal of Solid-State Circuits, 1995, Vol. 30, No. 6, pp.629-636. f. S.S. Rofail, Low-Voltage, Low-Power BiCMOS Digital Circuits, IEEE Journal of Solid State Circuits, May 1994, Vol. 29, No. 5, pp.572-579. 28. The work on Analysis and Optimization of BiCMOS Digital Circuits Structures, (S.H.K. Embabi, A. Bellaouar and M.I. Elmasry, IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp.676-679) has been referred to by:a. S.S. Rofail and M.I. Elmasry, "Analytical and Numerical Analyses of the Delay Time of BiCMOS Structures", IEEE Journal of Solid-State Circuits, Vol. 27, No. 5, May 1992, pp.834-839. b. M.S. Elrabaa and M.I. Elmasry, "Design and Optimization of Buffer Chains and Logic Circuits in a BiCMOS Environment", IEEE Journal of Solid-State Circuits, Vol. 27, No. 5, May 1992, pp. 792-801. c. T. Arnborg, "Performance Predictions of Scaled BiCMOS Gates Using Physical Simulation", IEEE Journal of Solid-State Circuits, Vol 27, No. 5, May 1992, pp.754-760. d. J.P. Harvey, M.I. Elmasry and B. Leung, "STAIC-An Interactive Framework for Synthesizing CMOS and BiCMOS Analog Circuits", IEEE Transactions on CAD, Vol. 11, No. 11, November 1992, pp.1402-1417. 29. The work on Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural Synthesis (C.H. Gebotys, M.I. Elmasry, Proc. of Design Automation Conference, San Francisco, June 1991, pp.2-7) has been referred to by:a. C.H. Gebotys, M.I. Elmasry, "Global Optimization Approach for Architectural Synthesis", IEEE Transactions on CAD of Integrated Circuits and Systems, Sep 1993, Vol. 12, No. 9, pp.1266-1278. b. M.J. Rim, R. Jain, "Lower-Bound Performance Estimation for the High-Level Synthesis Scheduling Problem", IEEE Transactions on CAD of Integrated Circuits and Systems, April 1994, Vol. 13, No. 4, pp.451-458. c. T.C. Wilson, N. Mukherjee, M.K. Garg, D.K. Banerji, "An ILP Solution for Optimum Scheduling, Module and Register Allocation, and Operation Binding in Datapath Synthesis", VLSI Design, 1995, Vol. 3, No. 1, pp.21-36. d. A. Sharma, R. Jain, "INSYN - Integrated Scheduling for DSP Applications", IEEE Transactions on Signal Processing, Aug 1995, Vol. 43, No. 8, pp.1966-1977. 30. The work on A Formal Approach to Control Unit Synthesis (M. Mahmood, F. Mavaddat, M.I. Elmasry, Proc. of IFIP Working Conference on Logic and Architectural Synthesis, Paris, France, June 1990, pp.126-135) has been referred to by:a. F. Mavaddat, "Datapath Synthesis as Grammar Inference", IFIP Transactions A-Computer Science and Technology, 1993, Vol. 22, pp.193-205. 31. The work on A Fast Learning Technique for the Multilayer Perceptron (W. Fakhr, M.I. Elmasry, Proc. of Int. Joint Conference on Neural Networks, (IJCNN 90), San Diego, CA., June 1990, pp.257-262) has been referred to by:a. C.S. Ho, C.C. Hsu, "Neural-Network-Based Blackboard Demon Subsystems", Applied Intelligence, June 1993, Vol. 3, No. 2, pp.143-158. b. S. Maruno, T. Kohda, H. Nakahira, S. Sakiyama, M. Maruyama, "Quantizer Neuron Model and Neuroprocessor-Named Quantizer Neuron Chip", IEEE Journal on Selected Areas in Communications, Dec 1994, Vol. 12, No. 9, pp.1503-1509. 32. The work on Scaling of Digital BiCMOS Circuits, (A. Bellaouar, S.H.K. Embabi and M.I. Elmasry, IEEE Journal of Solid State Circuits, Vol. 25, No. 4, August 1990, pp.932-941), has been referred to by:a. T. Arnborg, "Performance Predictions of Scaled BiCMOS Gates Using Physical Simulation", IEEE Journal of Solid-State Circuits, Vol. 27, No. 5, May 1992, pp.754-760. b. S.S. Rofail, M.I. Elmasry, "Temperature Dependent Characteristics of BiCMOS Digital Circuits", Vol. 40, No. 1, January 1993, pp.169-178. c. A. Masaki, "Possibilities of Deep-Submicrometer CMOS for Very-High-Speed Computer Logic", Proceedings of the IEEE, Sep. 1993, Vol. 81, No. 9, pp.1311-1324. d. S.S. Rofail, "Low-Voltage, Low-Power BiCMOS Digital Circuits", IEEE Journal of Solid State Circuits, May 1994, Vol. 29, No. 5, pp.572-579. e. Y.K. Seng, S.S. Rofail, "Full-Swing High-Speed CBICMOS Digital Circuit for Low-Voltage Applications", IEE Proceedings-Circuits Devices and Systems, Feb 1995, Vol. 142, No. 1, pp.8-14. f. A.H.M. Shousha, "Low-Voltage Full-Swing Non-Complementary BiCMOS Inverters", International Journal of Electronics, May 1995, Vol. 78, No. 5, pp.873-880. g. L.M. Castaner, R. Alcubilla, A. Benavent, "Bipolar-Transistor Vertical Scaling Framework", Solid-State Electronics, July 1995, Vol. 38, No. 7, pp.1367-1371. h. S.S. Rofail, Y.K. Seng, "1.1V Full-Swing Double Bootstrapped BiCMOS Logic Gate", IEE Proceedings-Circuits Devices and Systems, Feb 1996, Vol. 143, No. 1, pp.41-45. i. S.S. Rofail, Y.K. Seng, "Novel Low-Voltage BiCMOS Digital Circuits Employing a Lateral P-N-P BJT in a P-MOS Structure", IEE Proceedings-Circuits Devices and Systems, April 1996, Vol. 143, No. 2, pp.83-90. 33. The work on Novel Merged BiCMOS Circuit Structures, (A. Bellaouar and M.I. Elmasry, IEE Electronics Letters (Issue No. 19), September 1990, pp.1555-1556) has been referred to by:a. S. Liang, L.Z. Hou, T. Gu and C.A.T. Salama, "Latch Up in Physically Merged Bipolar MOS BiCMOS Structures", Electronics Letters, Vol. 27, No. 13, 1991, pp.1124-1126. b. S. Liang, L.Z. Hou, T. Gu and C.A.T. Salama, "Latch-up Modeling of BiCMOS Merged Bipolar MOS Structures", Solid-State Electronics, Vol. 35, No. 10, October 1992, pp.1461-1469. c. S.S. Rofail and M.I. Elmasry, "Temperature Dependent Characteristics of BiCMOS Digital Circuits", IEEE Transactions on Electron Devices, Vol. 40, No. 1, January 1993, pp.169-178. 34. The work on Experiments with Efficient Heuristic Algorithm for Local Microcode Generation (M. Mahmood, F. Mavaddat, M.I. Elmasry, Proc. of Int. Conference on Computer Design (ICCD 90), Cambridge, Mass., Sep 1990, pp.319-323) has been referred to by:a. F. Mavaddat, "Datapath Synthesis as Grammar Inference", IFIP Transactions A-Computer Science and Technology, 1993, Vol. 22, pp.193-205. 35. The work on Architectural Synthesis for DSP Silicon Compilers, (B.S. Haroun and M.I. Elmasry, IEEE Transactions on CAD, April 1989, pp.431-447), has been referred to by:a. P.P. Jain, S. Dhingra, J.C. Browne, "Bringing Top-Down Synthesis into the Real World", High Performance Systems-The Magazine for Technology Champions, Vol. 10, No. 7, 1989, pp.86. b. B.S. Haroun, M.I. Elmasry, "SPAID-An Architectural Synthesis Tool for DSP Custom Applications", IEEE Journal of Solid-State Circuits, Vol. 24, No. 2, February 1989, pp.426-435. c. Z. Peng, "Design of Clocking Schemes in High-Level Synthesis", Microprocessing and Microprogramming, Vol. 31, No. 1-5, pp.71-76. d. T.Y. Liu, Y.L. Lin, "A Data Path Allocator Based on Branch-and-Bound Search", Integration-The VLSI Journal, Vol. 11, No. 1, 1991, pp.43-66. e. C.T. Hwang, J.H. Lee, U.C. Hsu, "A Formal Approach to the Scheduling Problem in High-Level Synthesis", IEEE Transactions on CAD, Vol. 10, No. 4, April 1991, pp.464-475. f. B. Shung, R. Jain, K. Rimey, E. Wang, M.B. Srivastava, B.C. Richards, "An Integrated CAD System for Algorithm-Specific IC Design", IEEE Transactions on CAD, Vol. 10, No. 4, April 1991, pp.447-463. g. M. Potknojak, J. M. Rabaey, "Scheduling Algorithms for Hierarchical Data Control Flow-Graphs", International Journal of Circuit Theory and Applications, Vol. 20, No. 3, May-June 1992, pp.217-233. h. F.S. Tsai, Y.C. Hsu, "STAR-An Automatic Data Path Allocator", IEEE Transactions on CAD, Vol. 11, No. 9, September 1992, pp.1053-1064. i. L.E. Lucke, K.K. Parhi, "Data-Flow Transformations for Critical Path Time Reduction in High-Level DSP Synthesis", IEEE Transactions on CAD, Vol. 12, No. 7, July 1993, pp.1063-1068. j. K.R. Baker, A.J. Currie, and K.G. Nichols, "Multiple-Objective Optimization in a Behavioral Synthesis System", IEE Proceedings-G Circuits Devices and Systems, Vol. 140, No. 4, August 1993, pp.253-260. k. H.K. Kim, T.P. Barnwell, "A Design Synthesis System for Recursive DSP Algorithms Represented by Fully Specified Flow-Graphs", Journal of VLSI Signal Processing, Oct-Nov 1995 Vol. 11, No. 1-2, pp.35-50. 36. The work on SPAID: An Architectural Synthesis Tool for DSP Custom Applications (B.S. Haroun and M.I. Elmasry, IEEE Journal of Solid State Circuits, April 1989, pp.426-435) has been referred to by:a. T.F. Lee, A.C.H. Wu, Y.L. Lin, D.D. Gajski, "A Transformation-Based Method for Loop-Folding", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, April 1994, Vol. 13, No. 4, pp.439-450. b. J.L. Vanmeerbergen, P.E.R. Lippens, W.E.J. Verhaegh, A. Vanderwerf, "Very-High-Level Synthesis for High-throughput Applications", Journal of VLSI Signal Processing, Jan 1995, Vol. 9, No. 1-2, pp.89-104. c. H.K. Kim, T.P. Barnwell, "A Design Synthesis System for Recursive DSP Algorithms Represented by Fully Specified Flow-Graphs", Journal of VLSI Signal Processing, Oct-Nov 1995 Vol. 11, No. 1-2, pp.35-50. d. J.A. Huisken, A. Delaruelle, B. Egberts, P. Eeckhout, J. Vanmeerbergen, "Synthesis of Synchronous Communication Hardware in a Multiprocessor Architecture", Journal of VLSI Signal Processing, Dec 1995, Vol. 6, No. 3, pp.289-299. 37. The work on A Formal Language Model of Local Microcode Synthesis (M. Mahmood, F. Mavaddat, M.I. Elmasry, in Formal VLSI Specifications and Synthesis, VLSI Design Methods I, Proc. of the IMEC-IFIP Int. Workshop on Applied Formal Methods, Houthalen, Belgium, Luc. J.M. Claesen (ed.), Nov 1989, pp.23-41) has been referred to by:a. T. Kinoshita, M. Imai, T. Naoi, "A Procedure for Automatic Microprogram Synthesis Using E-Unification", Systems and Computers in Japan, Dec 1994, Vol. 25, No. 14,pp.1-11. 38. The work on Scaling of Digital BiCMOS Circuit Structures (A. Bellaouar, S.H.K. Embabi, M.I. Elmasry, Proc. of the IEEE Int. Electron Devices, Washington, D.C., Dec 1989, pp.437-440) has been referred to by:a. M.S. Elrabaa, M.I. Elmasry, "Design and Optimization of Buffer Chains and Logic Circuits in a BiCMOS Environment", IEEE Journal of Solid State Circuits, May 1992, Vol. 27, No. 5, pp.792-801. 39. The work on VLSI Design Synthesis with Testability (C.H. Gebotys, M.I. Elmasry, Proc. of Design Automation Conference, Anaheim, CA., June 1988, pp.16-21) has been referred to by:a. C. Nagel, "Synthesis for Testability by Synthesis Controlling", Microprocessing and Microprogramming, Sep 1993, Vol. 38, No. 1-5, pp.767-774. b. C.I.H. Chen, "Data-Path Synthesis Digital Electronics: 1. Memory Allocation", IEEE Transactions on Aerospace and Electronic Systems, Jan 1996, Vol. 32, No. 1, pp.2-15. c. C.I.H. Chen, "Data-Path Synthesis Digital Electronics: 2. Bus Synthesis", IEEE Transactions on Aerospace and Electronic Systems, Jan 1996, Vol. 32, No. 1, pp.16-33. 40. The work on Symbolic Layout for Bipolar and MOS VLSI, (K.S.B. Szabo, J.M. Leask, M.I. Elmasry, IEEE Transactions on CAD, Vol. 6, No. 2, March 1987), pp.202-210 has been referred to by:a. K.S.B. Szabo, J.M. Leask, M.I. Elmasry, "SYMPLE-A Symbolic Layout Tool for Bipolar and MOS VLSI", IEE Proceedings-L Solid-State and Electron Devices, Vol. 135, No. 2, 1988, pp.29-38. 41. The work on Generation of Noise by Electronic Iteration of the Logistic Map, (G.C. McGonigal and M.I. Elmasry, IEEE Transactions on Circuits and Systems, Vol. 34, No. 8, August 1987, pp.981-983) has been referred to by:a. M. Delgadorestituto, A. Rodriguezvasquez, S. Espejo, J.L. Huertas, "A Chaotic Switched Capacitor Circuit for 1/F Noise Generation", IEEE Transactions on Circuits and Systems I-Fundamental Theory and Applications, Vol. 39, No. 4, April 1992, pp.325-328. b. A. Rodriguezvazquez, M. Delgadorestituto, "CMOS Design of Chaotic Oscillators Using State Variables - A Monolithic Chua Circuit", IEEE Transactions on Circuits and Systems II - Analog and Digital Signal Processing, Oct 1993, Vol. 40, No. 10, pp.596-613. c. C.K. Tse, "Chaos from a Buck Switching Regulator Operating in Discontinuous Mode", International Journal of Circuit Theory and Applications, Jul-Aug 1994, Vol. 22, No. 4, pp.263-278. 42. The work on A VLSI Design Methodology with Testability Constraints (C.H. Gebotys, M.I. Elmasry, Proc. of the Canadian Conference on VLSI (CCVLSI 87), Winnipeg, Man., Oct 1987, pp.17-23) has been referred to by:a. T.A. Ly, J.T. Mowchenko, "Applying Simulated Evolution to High-Level Synthesis", IEEE Transactions on CAD of Integrated Circuits and Systems, March 1993, Vol. 12, No. 3, pp.386-409. 43. The Work on A VLSI Methodology with Testability Constraints, (C.H. Gebotys and M.I. Elmasry, CCVLSI 87, pp.17-23) has been referred to by:a. Paulin and Knight, "Forced Directed Scheduling for Behavioral Synthesis of ASICs", IEEE Trans. on CAD, June 1989, pp.661-679. 44. The Work on A VLSI Architecture and a Silicon Compiler for Designing Numerical Processors (D.J. Salomon, S. Sadler and M.I. Elmasry, VLSI Design, February 1985, pp.62-70) has been referred to by:a. A.V. Goldberg, S.S. Hirschhorn, K.J. Lieberherr, "Approaches Toward Silicon Compilation", IEEE Circuits and Devices Magazine, Vol. No. 3, 1985, pp.29-39. 45. The work on A Novel JCMOS Dynamic RAM Cell for VLSI Memories, (A.G. Eldin and M.I. Elmasry, IEEE Journal of Solid State Circuits, June 1985, pp.715-723) has been referred to by:a. W.C. Holton, R.K. Cavin, "A Perspective on CMOS Technology Trends", Proceedings of the IEEE, Vol. 74, No. 12, 1986, pp.1646-1668. b. A.G. Eldin and M.I. Elmasry, "Design Optimization of JCMOS Structures", IEEE Transactions on Electron Devices, Vol. 34, No. 10, October 1987, pp.2136-2145. c. A.G. Eldin and M.I. Elmasry, "New Dynamic Logic and Memory Circuit Structures for BiCMOS Technologies", IEEE Journal of Solid-State Circuits, Vol. 22, No. 3, 1987, pp.450-453. d. S. Kal and N.B. Chakrabarti, "Technology Compatibility and Circuit Complementarity of BiMOS", International Journal of Electronics, Vol. 68, No. 5, 1990, pp.675-692. 46. The work on Digital VLSI Systems, A Tutorial, Digital MOS Integrated Circuits, A Tutorial and Digital Bipolar Integrated Circuits, A Tutorial in the IEEE Press Book "Digital VLSI Systems", 1985, edited by M.I. Elmasry has been referred to by:a. K.S.B. Szabo, J.M. Leask and M.I. Elmasry, "Symbolic Layout for Bipolar and MOS VLSI", IEEE Transactions on CAD, Vol. 6, No. 2, 1987, pp.202-210. b. W. Alassadi, A.P. Jayasumana and Y.K. Malaiya, "Pass-Transistor Logic Design", International Journal of Electronics, Vol. 70, No. 4, 1991, pp.739-749. 47. The work on ICEWATER (P.A.D. Powell and M.I. Elmasry, "The ICEWATER Language and Interpreter", Proceedings from DAC, 1984, pp.98-102) has been referred to by:a. W.E. Cory, "Layla: A VLSI Layout Language", Proceedings from DAC, 1985, pp.245-265. 48. The work on SYMPLE (K.S.B. Szabo and M.I. Elmasry, Proceedings from the International Conference on Compiler Design, 1984, pp.474-479) has been referred to by:a. S.D. Posluszny, "SLS: An Advanced Symbolic Layout System for Bipolar and FET Design", Proceedings of ICCAD Conference, 1985, pp.346-348. 49. The work on Stick-Layout Notation for Bipolar VLSI, (M.I. Elmasry, VLSI Design, March/April 1983, pp.65-69) has been referred to by:a. K.S.B. Szabo, J.M. Leask and M.I. Elmasry, "Symbolic Layout for Bipolar and MOS VLSI", IEEE Transactions on CAD, Vol. 6, No. 2, 1987, pp.202-210. b. K.S.B. Szabo, J.M. Leask and M.I. Elmasry, "SYMPLE-A Symbolic Layout Tool for Bipolar and MOS VLSI", IEE Proceedings-I Solid-State and Electron Devices, Vol. 135, No. 2, 1988, pp.29-38. 50. The work on Digital Bipolar Integrated Circuits, (M.I. Elmasry, Editor, John Wiley, 1983) has been referred to by:a. Y.C. Yeung, "Novel Dynamic Random-Access Memory Cell Using 3 Diodes", IEE Proceedings-I Solid-State and Electron Devices, Vol. 133, No. 2, 1986, pp.61-62. b. K.S.B. Szabo, J.M. Leask and M.I. Elmasry, "Symbolic Layout for Bipolar and MOS VLSI", IEEE Transactions on CAD, Vol. 6, No. 2, February 1987, pp.202-210. c. I.N. Hajj and D. Saab, "Switch-Level Logic Simulation of Digital Bipolar Circuits", IEEE Transactions on CAD, Vol. 6, No. 2, February 1987, pp.251-258. d. E.W. Greeneich and K.L. McLaughlin, "Analysis and Characterization of BiCMOS for High-Speed Digital Logic", IEEE Journal of Solid-State Circuits, Vol. 23, No. 2, February 1988, pp.558-565. e. K.S.B. Szabo, J.M. Leask, M.I. Elmasry, "SYMPLE-A Symbolic Layout Tool for Bipolar and MOS VLSI", IEE Proceedings-I Solid-State and Electron Devices, Vol. 135, No. 2, April 1988, pp.29-38. f. W. Fang, "Accurate Analytical Delay Expressions for ECL and CML Circuits and Their Applications to Optimizing High-Speed Bipolar Circuits", IEEE Journal of Solid-State Circuits, Vol. 25, No. 2, February 1990, pp.572-583. g. S. Kal, N.B. Chakrabarti, "Technology Compatibility and Circuit Complementarity of BIMOS", International Journal of Electronics, Vol. 68, No. 5, 1990, pp.675-692. h. W. Fang, A. Brunnschweiler, P. Ashburn, "An Accurate Analytical BiCMOS Delay Expression and its Application to Optimizing High-Speed BiCMOS Circuits", IEEE Journal of Solid-State Circuits, Vol. 27, No. 2, February 1992, pp.191-202. i. M. Elrabaa, "Multiemitter BiCMOS CML Circuits", IEEE Journal of Solid-State Circuits, Vol. 27, No. 3, March 1992, pp.454-458. j. M.J. Rutka, R.F. Wolffenbuttel, "The Integrated Sensor Bus Interface in Silicon Based on the RS-422-A Standard", Sensors and Actuators A-Physical, Vol. 32, No. 1-3, April 1992, pp.499-506. k. M.J. Rutka, R.F. Wolffenbuttel, "D-Flip-Flop with a Programmable Delay with Power Consumption for Implementation in Smart Sensors", Sensors and Actuators A-Physical, Vol. 37. No. 8, June-August 1993, pp.600-606. 51. The work on Capacitance Calculations for VLSI, (M.I. Elmasry, IEEE ED Letters, Jan. 1982, p.6-7) has been referred to by:a. P. Yang and P.K. Chatterjee, "SPICE modeling for small Geometry MOSFET Circuits", IEEE Trans. on CAD, Feb. 1983, pp.169-182. b. L.A. Glasser and D.W. Dobberpuhl, "The Design and Analysis of VLSI Circuits", Addison-Wesley Publishers, 1985, p.160. c. R. Laubhan et al., "Interconnect Propagation Delay Characterization", Proc. of Custom IC Conf., 1986, pp.475-479. 52. The work on WATPAC (A. Teene, M.I. Elmasry and D. J. Roulston, IEEE Trans. on CAD, 1982, pp.927-933) has been referred to by:a. D.J. Roulston, "CAD of Bipolar Custom Chips Using a Coupled Process-Device-Circuit Simulation Package", 1983 Custom IC Conference, pp.229-232. 53. The work on Digital MOS Integrated Circuits, (M.I. Elmasry Editor, IEEE Press 1981) has been referred to by:a. M.I. Elmasry, L.R. Peterson, "A DOL CMOS Static Memory Cell", IEEE Journal of Solid-State Circuits, Vol. 16, No. 5, 1981, pp.466-471. b. M.I. Elmasry, "Interconnection Delays in MOSFET VLSI", IEEE Journal of Solid State Circuits, Vol. 16, No. 5, 1981, pp.585-591. c. M.I. Elmasry, "Capacitance Calculations in MOSFET VLSI", Electron Device Letters, Vol. 3, No. 1, 1982, pp.6-7. d. M.I. Elmasry, "Multidrain NMOS for VLSI Logic Design", IEEE Transactions on Electron Devices, Vol. 29, No. 4, 1982, pp.779-781. e. M.I. Elmasry, "Nanosecond NMOS VLSI Current Mode Logic", IEEE Transactions on Electron Devices, Vol. 29, No. 4, 1982, pp.781-784. f. B.J. Hosticka, U. Kleine, H. Vogt and G. Zimmer, "BiCMOS, Novel MOS Logic", Electronics Letters, Vol. 18, No. 21, 1982, pp.930-932. g. B.J. Hosticka, "Prospects of VLSI Readout", Nuclear Instruments and Methods in Physics Research Section A-Accelerators Spectrometers Detectors and Associated Equipment, Vol. 226, No. 1, 1984, pp.185-189. h. B.J. Hosticka, G. Zimmer, "Integration of Detector Arrays and Readout Electronics on a Single Chip", IEEE Transactions on Nuclear Science, Vol. 32, No. 1, 1985, pp.402-408. i. D. Ma, "A Physical and Spice-Compatible Model for the MOS Depletion Device", IEEE Transactions on CAD, Vol. 4, No. 3, 1985, pp.349-356. j. C.Y. Wu, J.S. Hwang, C. Chang and C.C. Chang, "An Efficient Timing Model for CMOS Combinational Logic Gates", IEEE Transactions on CAD, Vol. 4, No. 4, 1985, pp.636-650. k. K.S.B. Szabo, J.M. Leask and M.I. Elmasry, "Symbolic Layout for Bipolar and MOS VLSI", IEEE Transactions on CAD, Vol. 6, No. 2, 1987, pp.202-210. l. N. Hedenstierna, K.O. Jeppson, "CMOS Circuit Speed and Buffer Optimization", IEEE Transactions on CAD, Vol. 6, No. 2, 1987, pp.270-281. m. A.G. Eldin, M.I. Elmasry, "New Dynamic Logic and Memory Circuit Structures for BiCMOS Technologies", IEEE Journal of Solid-State Circuits, Vol. 22, No. 3, 1987, pp.450-453. n. F.S. Shoucair, "CMOS Logic Cell Switching Speed Thermal Characterization", Electronics Letters, Vol. 23, No. 9, 1987, pp.458-460. o. G. Ruan, J. Vlach and J.A. Barby, "Current-Limited Switch-Level Timing Simulator for MOS Logic Networks", IEEE Transactions on CAD, Vol. 7, No. 6, 1988, pp.659-667. p. C.Y. Wu, C. Li, J.S. Hwang, "Timing Macromodels for CMOS Static Set Reset Latches and Their Applications", IEE-Proceedings-E Computers and Digital Techniques, Vol. 135, No. 3, 1988, pp.151-160. q. Y.H. Yang, W.U. Cy, "Analysis and Modeling of Initial Delay Time and Its Impact on Propagation Delay of CMOS Logic Gates", IEE Proceedings-G Circuits Devices and Systems, Vol. 136, No. 5, 1989, pp.245-254. r. I. Derycke, A. Vancalster, J. Vanfleteren, J. Debaets, J. Doutreloigne, H. Desmet, P. Vetter, "2-MHz Clocked LCD Drivers on Glass", IEEE Journal of Solid State Circuits, Vol. 25, No. 2, 1990, pp.531-538. s. K. Lee, M. Shur, "PI-Heterostructure Field-Effect Transistors for VLSI Applications", IEEE Transactions on Electron Devices, Vol. 37, No. 8, 1990, pp.1810-1820. t. A.J. Alkhalili, Y. Zhu, D. Alkhalili, "A Module Generator for Optimized CMOS Buffers", IEEE Transactions on CAD, Vol. 9, No. 10, 1990, pp.1028-1046. u. O.A. Izosimov, I.I. Shagurin, V.V. Tsylyov, "Physical Approach to CMOS Module Self-Timing", Electronics Letters, Vol. 26, No. 22, 1990, pp.1835-1836. v. M.J. Edwards, "NMOS and CMOS Polysilicon Drive Circuits for Liquid-Crystal Displays", IEE Proceedings-Circuits Devices and Systems, Feb 1994, Vol. 141, No. 1, pp.50-55. w. T. Ichikawa, M. Sasaki, "A New Analytical Model of SRAM Cell Stability in Low-Voltage Operation", IEEE Transactions on Electron Devices, Jan 1996, Vol. 43, No. 1, pp.54-61. 54. The Work on Single Device Well MOSFET (E.Z. Hamdy, M.I. Elmasry and Y.A. El-Mansy, IEEE, Trans. on Electron Devices, March 1981, pp.322-328) has been referred to by:a. A. Roy and M.H. White, "A New Approach to Study Electron and Hole Charge Separation at the Semiconductor-Insulator Interface", IEEE Trans. on Electron Devices, 1989. 55. The work on SDW MOSFET Memory (M.I. Elmasry and E.Z. Hamdy, IEEE Journal of Solid State Circuits, April 1981, pp.80-85), has been referred to by:a. Electronics, "3 D MOSFETs Shrink Static RAM Cells and analog circuit blocks", May 5, l981, pp.39-40. b. Electronic Design, "Semiconductor Special-Digital", June 11, 1981, pp.102-103. c. R.W. Wilamowski, "Buried-channel MOS Transistor with Punched-Through", Solid-State Electronics, Vol. 27, 1984, pp.811-815. d. E. Harrari, "Novel Dynamic Merged Load Technology", Journal of Solid State Circuits, April 1985, pp.537-541. e. D.D. Shulman, "A Static Memory Cell-Based on the Negative Resistance of the Gate Terminal of P-N-P-N Devices", IEEE Journal of Solid State Circuits, June 1994, Vol. 29, No. 6, pp.733-736. 56. The work on Interconnection (M.I. Elmasry, Journal of Solid State Circuits, October 1981, pp.585-591) has been referred to by:a. R.J. Antione and G.W. Brown, "The Modeling of Resistive Interconnects for Integrated Circuits", Journal of Solid State Circuits, April 1983, pp.200-203. b. B. Randell and P.C. Treleaven, "VLSI Architecture", Prentice-Hall, p.178, 1983. c. A.J. Walton et al., "Numerical Simulation of Resistive Interconnects for IC", IEEE Journal of Solid State Circuits, Dec. 1985, pp.1252-1258. 57. The work on DOL Memory Cell M.I. Elmasry and L.R. Peterson, Journal of Solid State Circuits, October 1981, pp.466-471). has been referred to by:a. C.Y. Wu and Y.F. Liu, "A High Density MOS Static RAM Cell using the Lambda Bipolar Transistor", Journal of Solid State Circuits, April 1983, pp.222-224. 58. The work on BIMOS Structures (E.Z. Hamdy and M.I. Elmasry, "Bipolar Structures for BIMOS Technologies", IEEE Journal of Solid State Circuits, April 1980, pp.229-236), has been referred to by:a. E. Wildi, et al, "A Micropower, small input-to-output delay", High Voltage Bipolar Driver/Demultiplexer", IEEE Journal of Solid State Circuits, Feb. 1981, pp. 23-30. b. A.G. Milnes, "Semiconductor Devices and Integrated Electronics", Van Nostrand Reinhold, 1980. c. Y. Wang, "A new bipolar CMOS gate array for Analog- Digital applications", 1983 Custom IC Conf., pp.189-193. 59. The work on Scaling of SiMESFETs (G.V. Ram and M.I. Elmasry, IEEE ED Letters, Dec. 1980, p.259) has been referred to by:a. Y. Omura, "A simple model for short channel effects of a buried-channel MOSFET on the buried insulator", IEEE Trans. Electron Devices, November 1982, pp.1749-1755. b. K. Smith et al, "Constant Voltage Scaling of High Power IC s", Solid State Electronics, July 1983. c. C.S. Hou, C.Y. Wu, "A 2-D Analytical Model for the Threshold-Voltage of Fully Depleted Short Gate-Length SI-SOI MESFETs", IEEE Transactions on Electron Devices, Dec 1995, Vol. 42, No. 12, pp.2156-2162. 60. The Work on A Novel Single-Device Well MOSFET Gate (E.Z. Hamdy, M.I. Elmasry, and Y.A. El-Mansy, IEEE, IEDM Technical Digest, December 1979, pp.576-580) has been referred to by:a. A. Roy and M.H. White, "A New Approach to Study Electron and Hole Charge Separation at the Semiconductor-Insulator Interface", IEEE Trans. on Electron Devices, 1989. 61. The work on the modeling of IIL (S.S. Rofail, M.I. Elmasry and E.H. Heasell, "Functional Modeling of IIL - DC Analysis", IEEE Trans. on Electron Devices, March 1977, pp.234-241) has been referred to by researchers in the field, see for example:a. G.V. Ram and M.S. Tyagi, "A Simple Analytical Model for Estimating DC of Lateral p-n-p Transistors", IEEE Trans. on Electron Devices, January 1978, pp.62-64. b. A. Kolodny, "Current Gain of Shallow Junction Lateral Transistors", IEEE Trans. Electron Devices, June 1979, pp.987-989. c. P.C. Teixeira, "Efficient and Accurate Modeling of ^ I sup 2 L ^ ", the 1980 ICCC, pp.961-964. d. H. Koerselman and T. Poorter, "Excess Concentration, Electron and Hole Currents in an Epitaxial Emitter", Solid- State Electronics, January 1980, pp.28-32. 62. The work on Variable Program Microprocessor Systems Using Non-Volatile ERLIM Arrays (M.I. Elmasry, H.C. Card, Proc. of IEEE Power and Communication Conference, Oct 1976) has been referred to by:a. H.C. Card, M.I. Elmasry, "Functional Modeling of Non-Volatile MOS Memory Devices for CAD", Solid-State Electronics, October 1976, pp.863-870. 63. The Work on Modeling Non-Volatile MOS Memories (H.C. Card and M.I. Elmasry, Solid State Electronics, October 1976, pp.863-870) has been referred to by:a. Sze, Chapter 8. b. H.C. Card, E.L. Heasell, Modeling of channel Enhancement Effects on Write Characteristics of Famos Devices, Solid-State Electronics, Jan 1976, Vol. 19, No. 11, pp.965-968. c. F. Masszi, Computer-Aided-Design of MOS-LSI Circuits - Devices and Functional Models, Periodica Polytechnic-Electrical Engineering, 1978, Vol. 22, No. 1, pp.13-26. d. T. Ito, S. Hijiya, T. Nozaki, H. Arakawa, H. Ishikawa, M. Shinoda, Low- Voltage Alterable EAROM Cells With Nitride-Barrier Avalanche-Injection MIS (NAMIS), IEEE Transactions on Electron Devices, 1979, Vol. 26, No. 6, pp.906-913. e. M. Kojima, H. Kato, M. Gatto, Model for the Dry-Etching of Heavily- Doped N-Type Silicon By Atomic Flourine in the Absence of Ion- Bombardment, Journal of Applied Physics, June 1994, Vol. 75, No. 11, pp.7507-7513. f. S.C. Witczak, M. Gaitan, J.S. Suehle, M.C. Peckerar, D.I. Ma, The Interaction of Stoichiometry, Mechanical-Stress, and Interface Trap Density in LPCVD SI-RICH SINX-SI Structures, Solid-State Electronics, Oct 1994, Vol. 37, No. 10, pp.1695-1704. 64. The work on Non-Saturated Integrated Injection Logic (M.I. Elmasry, Electronics Letters, Feb 1975, pp.63-65) has been referred to by:a. C. Mulder, H.E.J. Wulms, "High-Speed Integrated Injection Logic", IEEE Journal of Solid State Circuits, 1976, Vol. 11, No. 3, pp.379-385. b. M.I. Elmasry, "Folded-Collector Integrated Injection Logic", IEEE Journal of Solid State Circuits, 1976, Vol. 11, No. 5, pp.644-647. c. F. Hennig, H.K. Hingarh, D. Obrien, P.W.J. Verhofstadt, "Isoplannar Integrated Injection Logic - High-Performance Bipolar Technology", IEEE Journal of Solid State Circuits, 1977, Vol. 12, No. 2, pp.101-109. d. J.L. Stone, "^ I sup 2 L ^ - Comprehensive Review of Techniques and Technology", Solid-State Technology, 1977, Vol. 20, No. 6, pp.42-48. e. B. Mazhari, H. Morkoc, "Intrinsic Gate Delay of SI/SIGE Integrated Injection Logic-Circuits", Solid-State Electronics, Jan 1995, Vol. 38, No. 1, pp.189-196. 65. The work on the analysis and modeling of IIL (M.I. Elmasry and R.D. Midha, "Load analysis of IIL", Electronic Letters, Feb. 1975, pp.68-69 has been referred to by researchers in the field, see for example:a. G.V. Ram and M.S. Tyagi, "A Simple Analytical Model for Estimating DC of Lateral p-n-p Transistors", IEEE Trans. on Electron Devices, January 1978, pp.62-64. b. A. Kolodny, "Current Gain of Shallow Junction Lateral Transistors", IEEE Trans. Electron Devices, June 1979, pp.987-989. c. P.C. Teixeira, "Efficient and Accurate Modeling of ^ I sup 2 L ^ ", the 1980 ICCC, pp.961-964. d. H. Koerselman and T. Poorter, "Excess Concentration, Electron and Hole Currents in an Epitaxial Emitter", Solid- State Electronics, January 1980, pp.28-32. 66. The work on Emitter Function Logic (M.I. Elmasry and P.M. Thompson, "Two-Level EFL Structures for Logic-in-Memory Computers", IEEE Trans. on Computers, March 1975, pp.250-258) has been referred to by researchers in the field, see for example:a. S.E. Skokan, "Emitter-Function- Logic Family for LSI", IEEE Journal of Solid State Circuits, October 1975, pp.356-361. b. R.J. Scavuzzo, "Digital Logic and Circuit Design for Improved Performance", 1980 ICCC, pp.693-696. 67. The work on Non-Saturated ILL in Circuit Design (M.I. Elmasry, Proc. of the European IEE Solid State Circuits Conference (ESSCIRC), Canterbury, England, Sep 1975, pp.20-21. (The Electronics Division of IEE) has been referred to by:a. J.L. Stone, "^ I sup 2 L ^ - Comprehensive Review of Techniques and Technology", Solid-State Technology, 1977, Vol. 20, No. 6, pp.42-48. 68. The work on folded-collector injection logic (M.I. Elmasry "Folded-Collector Integrated Injection Logic", IEEE, October 1975, pp.644-647) has been adopted as text book material (see for example Semiconductor Devices and Integrated Electronics by A.G. Milnes, published by Van Nostrand Reinhold, 1980 Fig. 814 a and b) and has been referred to by researchers in the field. See for example:a. C. Milder and H.E.J. Wilms, "High Speed Integrated Injection Logic", IEEE Journal of Solid State Circuits, June 1976, pp.379-385. b. C.G. Thornten and N.C. de Troye, the editors of the IEEE Journal of Solid State Circuits, special issue on IIL, IEEE JSSC, April 1977, pp.91-92. c. F. Hennig et al, "Isoplaner Integrated Injection Logic: A high Performance Bipolar Technology", IEEE Journal of Solid State Circuits, April 1977, pp.101-109. d. T.T. Dao, "Threshold IIL and Its Applications to Binary Symmetric Functions and Multivalued Logic", IEEE Journal of Solid State Circuits, April 1977, pp.463-472. e. T. Poorter, "Electrical Parameters, Static and Dynamic Response of IIL", IEEE Journal of Solid State Circuits, October 1977, pp.440-449. f. T.T. Dao, E.J. McCluskey and L.K. Russel, "On the performance of threshold gates", IEEE Trans. on Computers, December 1977, pp.1233-1241. g. S.A. Evans et al, "Fabrication of Integrated Injection Logic with Electron-Beam Lithography and Ion Implantation", IEEE Trans. on Electron Devices, April 1978, pp.402-407. h. J. Lohstroh, "ISL A Fast and Dense Low-Power Logic Mode in a standard Schottky Process", IEEE Journal of Solid State Circuits, June 1979, pp.585-590. i. S.A. Evans, "Scaling IIL for VLSI", IEEE Journal of Solid State Circuits, April 1979, pp.318-327. j. C.H. Han et al, "Feasibility of Substrate Fed Threshold Logic", Journal of Solid State Circuits, April 1983, pp.160-164. 69. The work on Realization of Arbitrary Logic Functions with Multi-Emitter Current Mode Structures (Proc. of Int. EE Conference, Toronto, Ont., Oct 1973, pp.170-171) has been referred to by:a. M.I. Elmasry, P.M. Thompson, "2-Level Emitter-Function Logic Structures for Logic-In-Memory Computers", IEEE Transactions on Computers, 1975, Vol. 24, No. 3, pp.250-258. 70. The work on Low Power Subnanosecond Logic Family for LSI (P.M. Thompson, M.I. Elmasry, Proc. of Int. EE Conference, Toronto, Ont., Oct 1973, pp.168-169) has been referred to by:a. M.I. Elmasry, "Logic Design Using EFL Structures", IEEE Transactions on Computers, 1976, Vol. 25, No. 9, pp.952-956.
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