Prof. Mohamed I. Elmasry  
 

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Refereed Journal Papers

(a) Submitted:

  1. Y. S. Abdalla and M. I. Elmasry, "15Gb/s MUX/DMUX in 0.185m CMOS Using a New
    All-Time-On Single-Ended CMOS Logic", Journal of VLSI.

(b) Accepted:

(c) Refereed Full Papers Published:

  1. Hassan Mostafa, Mohab Anis and M. I. Elmasry, "Statistical SRAM read access yield improvement using negative capacitance circuits.", IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21.1 (2013): 92-101.

  2. Hassan Mostafa, Mohab Anis and M. I. Elmasry, "NBTI and process variations compensation circuits using adaptive body bias.", IEEE transactions on semiconductor manufacturing 25.3 (2012): 460-467.

  3. Hassan Mostafa, Mohab Anis and M. I. Elmasry, "On-chip process variations compensation using an analog adaptive body bias (A-ABB)", IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20.4 (2012): 770-774.

  4. Hassan Mostafa, Mohab Anis and M. I. Elmasry, "Adaptive body bias for reducing the impacts of NBTI and process variations on 6T SRAM cells.", IEEE Transactions on Circuits and Systems I: Regular Papers 58.12 (2011): 2859-2871.

  5. Hassan Mostafa, Mohab Anis and M. I. Elmasry, "A bias-dependent model for the impact of process variations on the SRAM soft error immunity.", IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19.11 (2011): 2130-2134.

  6. Hassan Mostafa, Mohab Anis and M. I. Elmasry, "A novel low area overhead direct adaptive body bias (D-ABB) circuit for die-to-die and within-die variations compensation.", IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19.10 (2011): 1848-1860.

  7. Hassan Mostafa, Mohab Anis and M. I. Elmasry, "Novel timing yield improvement circuits for high-performance low-power wide fan-in dynamic OR gates.", IEEE Transactions on Circuits and Systems I: Regular Papers 58.8 (2011): 1785-1797.

  8. Hassan Mostafa, Mohab Anis and M. I. Elmasry, "Analytical soft error models accounting for die-to-die and within-die variations in sub-threshold SRAM cells.", IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19.2 (2011): 182-195.

  9. Hassan Mostafa, Mohab Anis and M. I. Elmasry, "A design-oriented soft error rate variation model accounting for both die-to-die and within-die variations in submicrometer CMOS SRAM cells.", IEEE Transactions on Circuits and Systems I: Regular Papers 57.6 (2010): 1298-1311.

  10. Ahmed Youssef, Mohab Anis and M. I. Elmasry, "On the Power Management of Simultaneous Multithreading Processors ", IEEE transactions on very large scale integration (VLSI) systems 18.8 (2010): 1243-1248.

  11. Kambiz Moez and Mohamed Elmasry, " A New Loss Compensation Technique for CMOS Distributed Amplifiers ", IEEE Transactions on Circuits and Systems II: Express Briefs 56.3 (2009): 185-189.

  12. H. Hassan, M. Anis and M. Elmasry, "Total Power Modeling in FPGAs Under Spatial Correlation ", IEEE transactions on very large scale integration (VLSI) systems 17.4 (2009): 578-582.

  13. Ahmed Youssef, Mohab Anis and M. I. Elmasry, "A Comparativ Study between Static and Dynamic Sleep Signal Generation Techniques for Leakage Tolerant Designs ", IEEE transactions on very large scale integration (VLSI) systems 16.9 (2008): 1114-1126.

  14. A. Ismail and M. Elmasry, " Analysis of The Flash ADC Bandwidth-Accuracy Tradeoff in Deep Submicron CMOS Technologies ", IEEE Transactions on Circuits and Systems II: Express Briefs 55.10 (2008): 1001-1005.

  15. A. Ismail and M. I. Elmasry, "A 6-bit 1.6GS/s Low Power Wide Band Flash ADC Converter in 0.13um CMOS Technology ", IEEE Journal of Solid-State Circuits 43.9 (2008): 1982-1990.

  16. Kambiz Moez and Mohamed Elmasry, "A Low-Noise CMOS Distributed Amplifier for Ultra- Wideband Applications ," IEEE Transactions on Circuits and Systems II, Vol. 55, no. 2, pp 126-130, Feb. 2008.

  17. M. I. Elmasry and Mohamed Masmoudi, "Editorial," Microelectronics Journal, vol 37, pp 1186-1187

  18. H. Hassan, M. Anis and M. Elmasry, "Low-Power Multithreshold MCML: Analysis, Design, and Variability," Microelectronics Journal, Vol 37/10, pp. 1097-1104, 2006.

  19. Kambiz K. Moez and M. I. Elmasry,"A Lumped-Element Analysis of CMOS Distributed Amplifiers Based on Image Impedance Technique, Microelectronics Journal, vol. 37, no. 10 , pp.

  20. Kambiz K. Moez and M. I. Elmasry, "Area-Efficient CMOS Distributed Amplifier using Compact CMOS Interconnects," IEE Electronics Letters, vol. 42, no. 17, pp 970-971, Aug. 2006.

  21. H. Hassan, M. Anis and M. Elmasry, "Impact of Technology Scaling and Process
    Variations on RF CMOS Devices," Microelectronics Journal, Vol 37/4, pp.275-282, 2006.

  22. Dalia A. El-Dib and M.I. Elmasry, "Memoryless Viterbi Decoder," IEEE Transactions on Circuits and Systems II.: Express Briefs, , vol. 52, no. 12, pp. 826-830, Dec. 2005.

  23. MOS current mode circuits: analysis, design, and variability
    Hassan, H.; Anis, M.; Elmasry, M.; Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume 13,  Issue 8,  Aug. 2005 Page(s):885 - 898

  24. Ahmed Youssef, Mohab Anis and Mohamed Elmasry, POMR: A Power Aware Interconnect Optimization Methodology, IEEE Transactions on VLSI systems, vol. 13,no. 3, pp. 297-307, March 2005.

  25. M. M. El Said, J. Sitch, and M. Elmasry, "An Electrically Pre-Equalized 10-Gb/s Duobinary Transmission System," J. Lightwave Technol. vol. 23, no.1, pp. 388-400, Jan. 2005.

  26. H. Hassan, M. Anis, and M. Elmasry, "Design and Optimization of MOS Current Mode Circuits for Parameter Variation", Integration, the VLSI Journal, Vol 38/3 pp 417-437, January 2005.

  27. Ayman M. ElSayed  and Mohamed I. Elmasry, "Phase-Domain Fractional-N Frequency Synthesizers" IEEE Transaction on Circuits and Systems - I: Vol 51, No. 3, March 2004, pp 440-449.

  28. Dalia A. El-Dib, M.I. Elmasry, "Modified Register-Exchange Viterbi Decoder for Low-Power Wireless Communications", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, February 2004, Vol.51, No.2, pp. 371-378.

  29. M. Anis, S. Areibi and M.I. Elmasry, "Design and Optimization of Multi-Threshold CMOS (MTCMOS) Circuits" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No 10, Oct. 2003, pp 1324-1342.

  30. Amr Fahim and M.I. Elmasry, "A Wideband Sigma-Delta Phase Locked Loop Modulator for Wireless Applications", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 39, No. 2, February 2003, pp. 53-62.

  31. A.M. Fahim and M.I. Elmasry, "A Fast Lock Digital Phase-Locked Loop Architecture for Wireless Applications", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 39, No. 2, February 2003, pp. 63-72.

  32. M.Anis, M.Allam and M.Elmasry, "Impact of Technology Scaling on CMOS Logic Styles," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 49, No. 8, August 2002, pp. 577-588.

  33. M. Elrabaa, M. Anis and M.I. Elmasry, "A Contention-Free DOMINO Logic for Scaled-Down CMOS", Institute of Electronics, Information and Communications Engineers Transactions on Electronics, (IEICE), Vol. E85-C, No. 5, May 2002, pp.1177-1181.

  34. M. Anis, M. Allam and M.I. Elmasry, "Energy Efficient Noise-Tolerant Dynamic Styles for Scaled-Down CMOS and MTCMOS Technologies", IEEE Transactions on VLSI Systems (Special Issue on Low-Power Electronics and Design), Vol. 10, No. 2, April 2002, pp. 71-78.

  35. A.M. Fahim and M.I. Elmasry, "Low-Power High-Performance Arithmetic Circuits and Architectures", IEEE Journal of Solid-State Circuits, Vol 37, No.1, January 2002, pp.90-94.

  36. M.M. Khellah and M.I. Elmasry, "A low-power high-performance current-mode multiport SRAM", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.5, October, 2001, pp.590-598.

  37. M.W. Allam and M.I. Elmasry, "Dynamic Current Mode Logic(DyCML), A New Low-Power High Performance Logic Style," IEEE Journal of Solid State Circuits, Vol. 36. No.3, March 2001, pp.550-558.

  38. M.W. Allam and M.I. Elmasry, "Dynamic Current Mode Logic(DyCML), A New Low-Power High Performance Logic Family," IEEE Journal of Solid State Circuits (Special Issue on CICC2000), December 2000, pp.1011-1021.

  39. N. Masoumi, S. Safavi-Naeini and M.I. Elmasry, "Fast and Efficient parametric modeling of contact-to-substrate coupling", IEEE Transactions, Computer-Aided Design of Integrated Circuits and Systems, Vol 19, Issue 11, November 2000, pp.1282-1292.

  40. M. Allam, M. Anis and M.I. Elmasry, "High-Speed Dynamic Logic Styles for Scaled-Down CMOS and MTCMOS Technologies", Proc. IEEE International Symposium on Low Power Electronics and Design, July 27-29, 2000, pp. 155-160.

  41. M.S. Obrecht, T. Manku and M.I. Elmasry, "Simulation of Temperature Dependence of Microwave Noise in MOS Transistors", Japanese Journal of Applied Physics, Vol. 39 Part 1, No. 4A, April 2000, pp.1690-1693.

  42. A. Bellaouar, M.S. Obrecht, A.M. Fahim and M.I. Elmasry, "Low-Power Direct Digital Frequency Synthesis for Wireless Communications", IEEE Journal of Solid State Circuits, Vol.35, Issue 3, March 2000, pp. 385-390.

  43. M.M. Khellah and M.I. Elmasry, "Current-Mode Circuit Techniques for Low-Power High-Performance Multi-Port SRAM Design", IEEE Transaction on VLSI Systems (Special Issue on Low-Power), August 1999, 14 pages.

  44. M. S. Obrecht, Edwin L. Heasell, J. Vlach and M.I. Elmasry, "Transient Phenomena in High Speed Bipolar Devices", VLSI Design, Vol.8 Nos.1-4, 1998, pp.475-480.

  45. D. Zhang and M.I. Elmasry, "VLSI Compressor Design with Applications to Digital Neural Networks", IEEE Transactions on VLSI Systems, Vol.5, No.2, June 1997, pp.230-233.

  46. D. Zhang and M.I. Elmasry, "A Structure Design Approach using a Priori Knowledge for Artificial Neural Networks". The International Journal of Modeling and Simulation, Vol.17, No.4, 1997, pp.328-335.

  47. D. Zhang and M.I. Elmasry, "A Parallel Digital Layered Perceptrons Implementation", Neural, Parallel & Scientific Computations, December 1996, pp.493-504.

  48. I.S. Abu-Khater, A. Bellaouar and M.I. Elmasry, "Circuit Techniques for CMOS Low-Power High-Performance Multipliers", IEEE Journal of Solid-State Circuits. October 1996, Vol. 31, No. 10, pp.1535-1546.

  49. E. Farag, M. Saleh, N. Elnady and M.I. Elmasry, "A Two-Level Hierarchical Mobile Network: Structure and Network Control", the International Journal of Reliability Quality and Safety Engineering, special issue on Reliability of Wireless Communication Systems, World Scientific Publishing Company. Vol 3, No. 4,1996, pp.325-351.

  50. D. Zhang and M.I. Elmasry, "Mapping Neural Networks into Systolic Arrays", Neural, Parallel & Scientific Computations, Dynamic Publishers, Atlanta, Vol. 4, No. 3, Sept. 1996, pp.341-352.

  51. R.X. Gu and M.I. Elmasry, "Power Dissipation Analysis and Optimization of Deep Submicron CMOS Digital Circuits", IEEE Journal of Solid State Circuits, March 1996, Vol. 31, Issue 5, pp.707-713.

  52. D. Zhang and M.I. Elmasry, "A Digital Perceptron Learning Implementation with Look-up Table Feedback Layer", The International Journal of Circuits, Systems and Computers, February 1996, Vol. 6, No. 1, pp.79-84.

  53. R.X. Gu and M.I. Elmasry, "All-N-Logic High-Speed True-Single-Phase Dynamic CMOS Logic", IEEE Journal of Solid State Circuits, February 1996, Vol. 31, Issue 2, pp.221-229.

  54. K.M. Sharaf and M.I. Elmasry,"Analysis and Optimization of Series-Gated CML and ECL High-Speed Bipolar Circuits", IEEE Journal of Solid State Circuits, February 1996, Vol. 31, No. 2, pp.202-211.

  55. S. Hessabi, M.Y. Osman and M.I. Elmasry, "Differential BiCMOS Logic Circuits: Fault Characterization and Design for Testability", IEEE Transactions on VLSI Systems, September 1995, Vol. 3, No. 3, pp.437-445.

  56. A. Bellaouar, M.I. Elmasry and S.H.K. Embabi, "Bootstrapped Full-Swing BiCMOS/BiNMOS Logic Circuits for 1.2-3.3V Supply Voltage Regime", IEEE Journal of Solid-State Circuits, June, 1995, Vol. 30, No. 6, pp. 629-636.

  57. R.X. Gu and M.I. Elmasry, "Novel High Speed Circuit Structures for BiCMOS Environment", IEEE Journal of Solid-State Circuits, May 1995, Vol. 30, No. 5, pp.563-570.

  58. M. Obrecht, M.I. Elmasry and E.L. Heasell, "TRASIM: Compact and Efficient Two-Dimensional Transient Simulator for Arbitrary Planar Semiconductor Devices", IEEE Transactions on Computer-Aided Design (IEEE Trans. CAD), Vol. 14, No. 4, April 1995, pp.447-458.

  59. D. Zhang and M.I. Elmasry, "A Programmable Neural Network Architecture Using BiCMOS Technology", Journal of Neural, Parallel and Scientific Computations, March 1995, Vol. 3, No. 1, pp.103-114.

  60. M.Y. Osman and M.I. Elmasry, "Semi-Deterministic Fault Independent Test Generation and its Impact on ATPG Performance", International Journal of Electronics, December 1994, Vol. 77, No. 6, pp. 1091-1099.

  61. D. Zhang, M. Kamel and M.I. Elmasry, "Fuzzy Clustering Neural Network (FCNN): Competitive Learning Algorithm and Parallel Architecture", Journal of Intelligent and Fuzzy Systems: Applications in Engineering and Technology, December 1994, Volume 2, Issue 4, pp.289-298.

  62. M.S. Obrecht, E.L. Heasell and M.I. Elmasry, "Comparison of Coupled and Decoupled Methods for Semiconductor Device Modeling", COMPEL, December 1994, vol.13, pp.785-794.

  63. A. Achyuthan and M.I. Elmasry, "Mixed Analog/Digital Hardware Synthesis of Artificial Neural Networks", IEEE Transactions on Computer Aided Design, September 1994, Vol. 13, No. 9, pp.1073-1087.

  64. A. Bellaouar, I.S. Abu-Khater, M.I. Elmasry and A. Chikima, "Full Swing Schottky BiCMOS/BiNMOS and the Effects of Operating Frequency and Supply Voltage Scaling", IEEE Journal of Solid-State Circuits, June 1994, Vol. 29, pp.693-700.

  65. M.Y. Osman and M.I. Elmasry, "Highly Testable Design of BiCMOS Logic Circuits", IEEE Journal of Solid-State Circuits, June, 1994, Vol. 29, No. 6, pp.671-678.

  66. K. Hassanein, L. Deng and M.I. Elmasry, "Analysis of the Correlation Structure for a Neural Predictive Model with Application to Speech Recognition", INNS Neural Networks Journal, February 1994, Vol. 7, No. 2, pp.331-339.

  67. M.S. Elrabaa, M.S. Obrecht and M.I. Elmasry, "Novel Low-Voltage Low-Power Full-Swing BiCMOS Circuits", IEEE Journal of Solid-State Circuits, February 1994, Vol. 29, No. 2, pp.86-93.

  68. D. Zhang, L. Deng and M.I. Elmasry, "Pipelined Architecture for Neural-Network-Based Speech Recognition", Int. Journal of Neural, Parallel and Scientific Computations, Vol. 2, No. 1, 1994, pp.81-92.

  69. K.M. Sharaf and M.I. Elmasry, "An Accurate Analytical Propagation Delay Model for High-Speed CML Bipolar Circuits", IEEE Journal of Solid State Circuits, January 1994, Vol. 29, No. 1, pp.31-45.

  70. M.S. Obrecht and M.I. Elmasry, "Speeding-up of convergence of Gummel iterations for transient simulation", COMPEL, December 1993, vol.12, pp.311-317.

  71. C. Gebotys and M.I. Elmasry, "A Global Optimization Approach for Architectural Synthesis", IEEE Transactions on CAD, September 1993, Vol. 12, No. 9, pp. 1266-1278.

  72. S.E. Rehan and M.I. Elmasry, "Modular Switched-Resistor ANN Chip for Character Recognition Using Novel Parallel VLSI Architecture", the Int. Journal of Neural, Parallel & Scientific Computations, 1993, Vol. 1, pp. 241-261.

  73. S.S. Rofail and M.I. Elmasry, "Temperature Dependent Characteristics of BiCMOS Digital Circuits", IEEE Transactions on Electron Devices, January 1993, Vol. 40, No. 1, pp.169-178.

  74.  J.P. Harvey, M.I. Elmasry and B. Leung, "STAIC: An Interactive Framework for Synthesizing CMOS and BiCMOS Analog Circuits", IEEE Trans. on CAD, November 1992, Vol. 11, No. ll, pp.1402-1417.

  75.  S.S. Rofail and M.I. Elmasry, "Analytical and Numerical Analyses of the Delay Time of BiCMOS Structures", IEEE Journal of Solid State Circuits, May 1992, Vol. 27, No. 5, pp.834-839.

  76. M. Elrabaa and M.I. Elmasry, "Design and Optimization of Buffer Chains and Logic Circuits in a BiCMOS Environment", IEEE Journal of Solid State Circuits, May 1992, Vol. 27, No. 5, pp.792-801.

  77. C.H. Gebotys and M.I. Elmasry, "Optimal Synthesis of High Performance Architectures", IEEE Journal of Solid State Circuits, March 1992, Vol. 27, No. 3, pp.389-397.

  78. B.A. White and M.I. Elmasry, "The Digi-Neocognitron: A Digital Neocognitron Neural Network Model for VLSI", IEEE Transactions on Neural Networks, January 1992, Vol. 3, No. 1, pp.73-85.

  79. A.S. Bhogal, R.E. Seviora and M.I. Elmasry, "Towards Connectionist Production Systems", Expert Systems with Applications, 1991, Vol. 2, No. 1, pp.3-14.

  80. A. Bellaouar, S.H.K. Embabi and M.I. Elmasry, "Scaling of Digital BiCMOS Circuits", IEEE Journal of Solid State Circuits, August 1990, Vol. 25, No. 4, pp.932-941.

  81. C.H. Gebotys, and M.I. Elmasry, "Integration of Algorithmic VLSI Synthesis with Testability Incorporation", IEEE Journal of Solid State Circuits, April 1989, Vol. 24, Issue 2, pp.409-416.

  82. B.S. Haroun and M.I. Elmasry, "SPAID: An Architectural Synthesis Tool for DSP Custom Applications", IEEE Journal of Solid State Circuits, April 1989, pp.426-435.

  83. B.S. Haroun and M.I. Elmasry, "Architectural Synthesis for DSP Silicon Compilers", IEEE Trans. on CAD, April 1989, pp.431-447.

  84. K.S.B. Szabo, J. Leask and M.I. Elmasry, "SYMPLE: A Symbolic Layout Tool for Bipolar and MOS VLSI", IEE Proceedings, April 1988, pp.29-38.

  85. M.I. Elmasry, "The Future Role of Microelectronics", Kuwait Computer Alwattan, [Invited overview], March 1988, pp. 20-25.

  86. A.G. Eldin and M.I. Elmasry, "Design Optimization of JCMOS Structures", IEEE Trans. on Electron Devices, October 1987, ED-34, No. 10, pp.2136-2145.

  87. K.S.B. Szabo, J. Leask and M.I. Elmasry, "Symbolic Layout for Bipolar and MOS VLSI", IEEE Trans. on Computer Aided Design, CAD-6 (No. 2), March 1987, pp.202-210.

  88. F. ElGuibaly and M.I. Elmasry, "Sticks Layout Notation for MESFETs and Refractory-Metal FETs", VLSI Systems Design, February 1986, pp.88-96.

  89. A.G. Eldin and M.I. Elmasry, "A Novel JCMOS Dynamic RAM Cell for VLSI Memories", IEEE Journal of Solid State Circuits, June 1985, pp.715-723.

  90. M.I. Elmasry, Digital VLSI Systems: A Tutorial, A tutorial in the IEEE Press Book "Digital VLSI Systems", edited by M.I. Elmasry, 1985.

  91. M.I. Elmasry, Digital MOS Integrated Circuits: A Tutorial, in the IEEE Press Book "Digital VLSI Systems", edited by M.I. Elmasry, 1985.

  92. M.I. Elmasry, Digital Bipolar Integrated Circuits: A Tutorial, in the IEEE Press Book "Digital VLSI Systems", edited by M.I. Elmasry, 1985.

  93. D.J. Salomon, S. Sadler and M.I. Elmasry, "A VLSI Architecture and a Silicon Compiler for Designing Numerical Processors", VLSI Design, February 1985, pp.62-70.

  94. A. Silburt, A.R. Boothroyd and M.I. Elmasry, "A Novel Multiple Threshold MOSFET Structure for A/D and D/A Conversion", IEEE Journal of Solid State Circuits, October 1984, pp.794-802.

  95. A.R. Teene, M.I. Elmasry and D.J. Roulston, "WATPAC; A Computer Aided Design Package for Digital Bipolar Integrated Circuits", IEEE Trans. on CAD, December 1982, pp.927-933.

  96. E.Z. Hamdy and M.I. Elmasry, "SDW MOSFETs in LSI Analog Circuit Design", IEEE, Journal of Solid State Circuits, February 1982, pp.2-8.

  97. E.A. Vopni, M.I. Elmasry and J.V. Hanson, "A CMOS Time -Multiplexed Digital Filter for Vocoder Applications", Canadian Electrical Engineering Journal, January 1982, pp.7-13.

  98. M.I. Elmasry, "Inter Connection Delays in MOSFET VLSI", IEEE Journal of Solid State Circuits, October 1981, pp.585-591.

  99. M.I. Elmasry, Digital MOS Integrated Circuits: A Tutorial in the IEEE Press Book "Digital MOS Integrated Circuits", Edited by M.I. Elmasry, IEEE Press N.Y., 1981, pp.4-27.

  100. M.I. Elmasry and L.R. Peterson, "A DOL CMOS Static Memory Cell", IEEE Journal of Solid State Circuits, October 1981, pp.466-471.

  101. M.H. Elsaid and M.I. Elmasry, "Scaling Merged SDW MOSFETs for VLSI", Solid State Electronics, October l981, pp.967-973.

  102. M.I. Elmasry and E.Z. Hamdy, "SDW MOSFET Static Memory Cell", IEEE Journal of Solid State Circuits, April l981, pp.80-85.

  103. M.I. Elmasry and D.J. Roulston, "Base Component of Gain and Delay Time in Base Implemented Bipolar Transistors", Solid-State Electronics, April 1981, pp.371-375.

  104. E.Z. Hamdy, M.I. Elmasry and Y.A. El-Mansy, "Single-Device -Well MOSFETs", IEEE Trans. on Electron Devices, March 1981, pp.322-327.

  105. M.I. Elmasry, "On the DC Characteristics of MOS Differential Stages", Canadian Electrical Engineering Journal, January 1981, pp.29-33.

  106. E.Z. Hamdy and M.I. Elmasry, "Bipolar Structures for BIMOS Technologies", IEEE Journal of Solid State Circuits, April 1980, pp.229-236.

  107. M.I. Elmasry, "Logic Design using Emitter-Function-Logic", IEEE Trans. on Computers, September 1979, pp.952-956.

  108. S.S. Rofail, M.I. Elmasry and E.L. Heasell, "Functional Modeling of Integrated Injection Logic - Transient Analysis", IEEE Trans. on Electron Devices, September 1978, pp.1120-1125.

  109. M.I. Elmasry, M.H. Elsaid, D.J. Roulston and S.S. Rofail "Integrated Injection Logic for a Linear/Digital LSI Environment", IEEE Trans. on Electron Devices, March 1978, Vol. ED 25, No. 3., pp.351-357.

  110. M.I. Elmasry and A.G. Eldin, "Functional Modeling of Floating Substrate MOS Structures", the International Journal of Electronics, 1977, Vol. 43, No. 5, pp.433-444.

  111. S.S. Rofail, M.I. Elmasry and E. L. Heasell, "Functional Modeling of Integrated Injection Logic --- DC Analysis", IEEE Trans. on Electron Devices, March 1977, pp.234-241.

  112. H.C. Card and M.I. Elmasry, "Functional Modeling of Non Volatile MOS Memory Devices for CAD", Solid-State Electronics, October 1976, pp.863-870.

  113. M.I. Elmasry, "Logic Design Using Emitter-Function Logic", IEEE Trans. on Computers, September 1976, pp.952-956.

  114. M.I. Elmasry and P.M. Thompson, "Two-Level EFL Structures for Logic-in-Memory Computers", IEEE Trans. on Computer, March 1975, pp.250-258.

  115. M.I. Elmasry and P.M. Thompson, "Logic Partition for Multiemitter Two-Level Structures", IEEE Trans. on Circuit Theory, May 1974, pp.354-359.

 
 
 
     
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