Publications

• Book and book chapters
1. M. Sachdev, “Digital CMOS Fault Modeling and Inductive Fault Analysis,” pp. 43 -84, chapter in book, Integrated Circuit Manufacturability: The Art of Process and Design Integration, IEEE Press, ISBN 0-7803- 3447-7, 1998.
2. M. Sachdev, “Defect Oriented Testing,” pp. 15 - 54, chapter in book, Analog and Mixed-Signal Test, Printice Hall, ISBN 0-13-786310-1, 1998.
3. M. Sachdev, “Defect Oriented Testing for CMOS Analog and Digital Circuits,” Kluwer Academic Publishers, ISBN 0-7923-8083-5, 1998, Complete book, pp. 308.
• Patents
1. Manoj Sachdev, “IDDQ Testable Programmable Logic Array,” US Patent No. 6127838, granted October 2000.
2.  J. Tsachnz, M. Sachdev, S. Narendra and V. De, “High Performance Flip- flops with SNP,” Invention disclosure,  December 1999.
3. M. Sachdev, S. Narendra, J. Tsachnz and V. De, “Novel Dual Edge Triggered Flip-flops,” Invention disclosure,  November 1999.
4. M. Sachdev and Narendra Siva, “Impulse Triggered Flip-flops,” Invention disclosure,  November 1999.
5. M. Sachdev, “Testing control signals in A/D converters”, US Patent No. 5,969, 653, granted Oct. 1999.
6. Manoj Sachdev, “A Built-In Design For Test Strategy for High Speed Testing”, Invention disclosure, University of Waterloo. July 1998.
7. Manoj Sachdev, “Fault-Tolerant Memory Address Decoder”, US Patent No. 5,831,986, granted November 1998.
8. Manoj Sachdev, “MOS Master-slave Flip-flop with Reduced Number of Pass Gates”, US Patent No. 5,831,463, granted November 1998.
9. Manoj Sachdev and Botjo Atzema, “Method for Testing Electronic Circuit by Logically Combining Clock Signals and an Electronic Circuit Provided with Facilities for such Testing”, U.S. Patent 5,781,025, granted July 1998.
10. Manoj Sachdev and Botjo Atzema, “IDDQ Testing of Bias Generator Circuit,” U.S. Patent No. 5,751,141, May 1998.
11. Manoj Sachdev, ‘‘Separate IDDQ Testing of Signal Path and Bias Path in an IC’’, U.S. Patent No. 5,625,300, April 1997.
12. Manoj Sachdev, ‘‘Memory Testing Through Cumulative Wordline Activation”, U.S. Patent No. 5,495,448, February 1996.
13. Manoj Sachdev, “IDDQ Testable RAM”, U.S. Patent No. 5,491,665, February 1996.
14. Manoj Sachdev, ‘‘Testing Sequential Logic Circuits upon Changing into Combinatorial Logic Circuits’’, European Patent application no. 93202027.4, July 1993. (granted in Taiwan).
• Journal papers
1.  O. Semenov, A. Pradzynski, and M. Sachdev, “Impact of Gate Induced Drain Leakage on Overall Leakage of sub-micron CMOS VLSI Circuits,” IEEE Transactions on Semiconductor Manufacturing, Accepted for publication, October 2001.
2. M. Sachdev, “Current-Based Testing for Deep Submicron VLSIs,” IEEE Design & Test of Computers,  pp. 77 - 84, March 2001.
3. M. Shashaani and M. Sachdev, “Detection of High Performance Failures with a Low Performance VLSI Tester,” IEEE Transactions on VLSI, (16 pages), Accepted for publication, December 2000.
4. H. Speek, H.G. Kerkhoff, M. Sachdev and M. Shashaani, “Design for Testability for High-Speed Digital ICs,” accepted for publication, Journal of Electronic Testing: Theory and Applications (JETTA), Kluwer Academic Publishers, to appear in 2001.
5. M. Sachdev and Hans Kerkhoff, “IDDQ Testable PLA Configurations and Their Design Implications,” IEEE Design & Test of Computers, pp. 58 - 65, April- June 1999.
6. R. Rosing, H. Kerkhoff, R. Tangelder, and M. Sachdev, “Off-Chip Diagnosis of Aperture Jitter in Full Flash Analog to Digital Converters, Journal of Electronic Testing: Theory and Applications (JETTA), 14, pp. 67 - 74, June 1999.
7. M. Sachdev, “Open Defects in CMOS RAM Address Decoders,” IEEE Design & Test of Computers, pp. 26-33, June 1997.
8. M. Sachdev, “Separate IDDQ Testing of Signal Path and Bias Path in CMOS ICs”, Journal of Electronic Testing: Theory and Applications (JETTA), vol. 8, pp. 203-214, June 1996.
9. M. Sachdev, ‘‘Testing Defects in Scan Chains’’, IEEE Design and Test of Computers, pp. 45-51, winter 1995.
10. M. Sachdev, ‘‘A Realistic Defect Oriented Testability Methodology for Analog Circuits,’’ Journal of Electronic Testing: Theory and Applications (JETTA), no. 3, pp. 265-276, June 1995.
11. M. Sachdev, ‘‘Reducing the CMOS RAM Test Complexity with IDDQ and Voltage Testing,’’ Journal of Electronic Testing: Theory and Applications (JETTA), No. 2, pp. 191-202, April 1995.
12. E. Bruls, M. Sachdev, and K. Baker, Comments on ‘‘Totally self-checking CMOS Circuit Design for Breaks and Stuck-on Faults,’’ Journal of Solid-State Circuits, pp. 1056-1057, 1993.
• Refereed conference papers
1. A. Vassighi, O. Semenov, and M. Sachdev, “Impact of Leakage Current on Burn-in Test Environment for Sub-micron Technologies,” IEEE Yield Optimization and Test Workshop, November 2001.
2. O. Semenov, A. Pradzynski, and M. Sachdev, “Contribution of Gate Induced Drain Leakage on Overall Leakage and Yield of sub-micron Digital CMOS VLSIs,” IEEE International Integrated Reliability Workshop, October 2001.
3. M. Elgebaly, and M. Sachdev, “A Sub-0.5 V Dynamic Threshold PMOS (DTPMOS) Scheme for Low Voltage Applications,” International Conference on Microelectronics, October 2001.
4. J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev and V. De, “Comparative Delay and Energy of Single Edge-Triggered & Dual Edge Triggered Pulsed FFs for High Performance Microprocessors,” Proc. of International Symposium on Low Power Electronics and Design, August 2001.
5. N. Masoumi, S. Safavi-Naeini, M.I. Elmasry and M. Sachdev, “A Methodology for Analysis of Substrate Coupling in VLSI Using an Image Based Green’s Function for Modeling,” IEEE Electro/Information Technology Conference, Rochester, Michigan, June 2001.
6. M. Nummer, and M. Sachdev, “High Performance Circuit Testing at Arbitrarily Low Clock Frequency,” Proc. of IEEE International VLSI Test Symposium, pp. 68 - 74, May 2001.
7. O. Semenov, and M. Sachdev, “Technology Scaling and Detection of Bridging Fault Resistance,” Proc. of IEEE International Defect Based Test Methods Workshop, pp. 45 - 50, April 2001.
8. A. Keshavarzi, K. Roy, M. Sachdev, C. Hawkins, K. Somyanath and V. De, “Multiple-Parameter CMOS IC Testing with Increased Sensitivity for IDDQ,” Proc. of IEEE International Test Conference, Atlantic City, pp. 1051 - 1059, USA, September 2000.
9. W. M. Chung, and M. Sachdev, “A Comparative Analysis of Dual Edge Triggered Flip-flops,” IEEE CCECE 2000, pp. 564 - 569, May 2000, Halifax, Canada.
10. O. Semenov, and M. Sachdev, “Impact of Technology Scaling on Bridging Fault Detection in Sequential and Combinational CMOS Circuits,” IEEE CCECE 2000, pp. 199 - 203, May 2000, Halifax, Canada.
11. H. Speek, H.G. Kerkhoff, M. Sachdev and M. Shashaani, “Bridging the Testing Speed Gap: Design for Delay Testability,” Proceedings of IEEE European Test Workshop, May 2000, Portugal.
12. H. Speek, H.G. Kerkhoff, M. Shashaani, and M. Sachdev, “A Low Speed BIST Framework for High Speed Circuit Testing,” Proc. of IEEE VLSI Test Symposium, pp. 349- 355, May 2000, Montreal, Canada.
13. O. Semenov and M. Sachdev, “Technology Scaling and Bridging Fault Detection,” IEEE International Workshop on Current and Defect Based Testing, pp. 36-41, April 2000, Montreal, Canada.
14. M. Shashaani and M. Sachdev, “A Design For Test Technique for High Performance Circuit Testing,” IEEE International Test Conference, Atlantic City, September 1999, pp. 276-285, USA.
15. M. Shashaani and M. Sachdev, “A Comparative Analysis of High Speed Digital Test Techniques,” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineering, Edmonton, May 1999, pp. 379- 384, Canada.
16. R.J.W.T. Tangelder, H. de Vries, R.Rosing, H.G. Kerkhoff, M. Sachdev, “Jitter and Decision-level Noise Separation in A/D Converters,” Proceedings of 16th IEEE Intstrumentation and measurement Technology Conference, May 1999, pp. 1558 - 1562.
17. M. Sachdev, “Feasibility of Deep Sub-micron Current Testing: Issues & Options,” IEEE International Workshop on IDDQ Testing, April 1999, Dana point, USA (Invited paper).
18. M. Sachdev, P. Jansen, and V. Zieren, “Defect Detection with Transient Current Testing and its Potential for Deep Sub-micron ICs,” Proceedings of IEEE International Test Conference, pp. 204-213, October, 1998, Washington DC, USA (Honorable Mention Award).
19. R. Rosing, H. Kerkhoff, R. Tangelder, and M. Sachdev, “Jitter Diagnosis in Analogue-to-Digital Converters, Proceedings of IEEE International Mixed-Signal Test Workshop, pp. 215-220, June 1998, Den Hague, The Netherlands.
20. R. Rosing, H. Kerkhoff, R. Tangelder, and M. Sachdev, “Off-Chip Diagnosis of Aperture Jitter in Full Flash Analog to Digital Converters, Proceedings of IEEE European Test Workshop, May 1998, Barcelona, Spain.
21. M. Sachdev and H. Kerkhoff, “IDDQ Testable Dynamic PLAs,” Proceedings of IEEE International Workshop on IDDQ Testing,” November 1997, pp. 17-22, Washington DC, USA.
22. H.G. Kerkhoff, M. Sachdev, and H. Speek, “Accurate Delay-Fault ATPG in High-Speed CPLDs”, Proceedings of IEEE European Test Workshop, June 1997, Italy.
23. M. Sachdev, “Deep Sub-micron IDDQ Testing: Issues and Solutions”, Proceedings of IEEE European Design and Test Conference, pp. 271- 278, 1997, Paris, France (Best paper award).
24. M. Sachdev, “Deep Sub-micron IDDQ Test Options,” Proceedings of IEEE International Test Conference, 1996, pp. 942, Washington DC, USA.
25. R. Peset Llopis, and M. Sachdev, “Low Power, Testable Dual Edge Triggered Flip-Flops”, Proceedings of IEEE International Symposium on Low Power Electronics and Design, August 1996, Montray, USA.
26. H. Kerkhoff, M. Sachdev, G. van Brakel, and C. Klaasen, “Delay-Fault ATPG for High-Speed Electrically Erasable PLDs”, Proceedings of IEEE European Test Workshop, June 1996, Montpellier, France.
27. M. Sachdev, ‘‘Test and Testability Techniques for Open Defects in RAM Decoders”, Proceedings IEEE European Design & Test Conference, March 1996, pp. 428-434, Paris, France.
28. M. Sachdev, “IDDQ Test and Diagnosis in Deep Sub-micron,” Proceedings of 1st International Workshop on Current Testing, pp. 84-89, October 1995.
29. M. Sachdev, ‘‘IDDQ and Voltage Testable CMOS Flip-flop configurations,’’ Proceedings of International Test Conference, pp. 534-543, October 1995.
30. M. Sachdev and B. Atzema, ‘‘Industrial Relevance of Analog IFA: A Fact or a Fiction,’’ Proceedings of International Test Conference, pp. 61-70, October 1995.
31.  V. Kaal, H.Kerkhoff, M. Sachdev, “Rule Driven Mixed-Signal Test Generation,” Proceedings of International Mixed Signal Testing Workshop, June 1995.
32. B. Atzema, E. Bruls, M. Sachdev, and T. Zwemstra, “Computer Aided Testability Analysis for Analog Circuits,” Proceedings of workshop on Advances in Analog Circuit Design, April 1995. (invited paper).
33. F.C.M. Kuijstermans, M. Sachdev, and A.P. Thijssen, ‘‘Defect Oriented Test Methodology for Complex Mixed-Signal Circuits,’’ Proceedings of European Design and Test Conference, pp. 18-23, March 1995.
34. M. Sachdev, “Reducing the Test Time for RAMs,” Philips Research Bulletin on IC Design,  No. 21, pp. 10-11, September 1994.
35. M. Sachdev, ‘‘Defect Oriented Analog Testing: Strengths and Weaknesses’’, Proceedings of European Solid State Circuits Conference, pp. 224-227, September 1994.
36. M. Sachdev, ‘‘Transforming Sequential Logic in Digital CMOS ICs for Voltage and IDDQ Testing,’’ Proceedings of European Design and Test Conference, pp. 361-365, 1994.
37. M. Sachdev, ‘‘Catastrophic Defect Oriented Testability Analysis of a Class AB Amplifier,’’, Proceedings of International Workshop on Defect and Fault Tolerance in VLSI systems, pp. 319-326, 1993.
38. M. Sachdev, and M. Verstraelen, ‘‘Development of a Fault Model and Test Algorithms for Embedded DRAMs’’, Proceedings of International Test Conference, pp. 815-824, October 1993.
39. M. Sachdev, ‘‘Flip-flop Fault Model for CMOS ASIC Libraries’’, VLSI Design Conference, London, Oct. 1991.
40. M. Sachdev, ‘‘A Formal Method of Designing Corecell Architecture for Channelless Gate Arrays’’, National symposium on circuits and systems, Roorkee (India) November 1989.
41. M. Sachdev, ‘‘A Novel Gate Array Corecell Architecture for CMOS Channelless Gate Arrays’’, Proceedings of 31st Midwest symposium on circuits and systems, St. Louis, August 1988.
• Non-Refereed publications
1.   M. Sachdev, ‘‘Better Testable CMOS Flip-Flops,’’ Philips Research Newsletter, No. 155, April 1995.
• Links
• International Technology Roadmap for Semiconductors (ITRS)