60 GHz DAT based Power Amplifer Design in 65-nm CMOS


Abstract:

An ever increasing demand for data rate and bandwidth in wireless communication has pushed research in recent years to seek a solution by exploiting unlicensed bands in the millimeter wave frequencies. CMOS technologies at the sub-micron size exhibiting large transition frequencies, fT , have brought advantages such as low-power consumption and low-cost which rivals its alternatives. However, the extremely low breakdown voltage brings about challenges in Power Ampli er designs such as a high impedance transfor- mation ratio and achieving good Power Added Eciency (PAE). This project is based on the study and design of a CMOS class AB Power Ampli er based on the Distributed Active Transformer (DAT) Architecture. A comparison of the DAT structure to a con- ventional structure will be made to motivate the study. This paper will document the design steps and considerations for the impedance transformers, the DAT, and the ac- tive circuits for the amplifer, based on papers [1] and [2]. The design will be evaluated through analysis and simulations (EM and circuit based) carried out in the Advanced System Design (ADS) environment.