Last Update: August 2022.

Current Projects

A PRedictable Execution Model (PREM) for Real-Time Applications

We introduced a software-based, PRedictable Execution Model (PREM) for real-time tasks, which greatly increases the time predictability of the memory and communication subsystems in embedded hardware architectures. Under PREM, each task's execution is divided into a sequence of segments. A specialized compiler modifies the code of each predictable interval to prefetch all required data from main memory at the beginning of each segment. After the prefetching is complete, the segment can then execute without suffering any cache miss. Once the segment is complete, modified data is written back to main memory. Combining PREM with a suitable system-level scheduler allows us to eliminate unpredictable contention for access to memory elements. The validity of the model has been demonstrated of a variety of task models and embedded architectures.

Duetto: Latency Guarantees at Minimal Performance Cost

High-performance computer architectures are normally designed to optimize average-case performance. However, such optimizations often rely on speculative features, such as prefetching and request reordering, which can adversely affect worst-case scenarios. For this reason, it has been difficult to provide timing guarantees on the latecy of memory requests in modern SoC platform. As a consequence, researchers in the real-time domain have devised a set of architectures (including caches, buses, main memory controllers...) specifically designed to provide tight latecy bounds. However, such bounds are generally achieved by disabling most of the optimizations targeted at average performance.

To overcome the fundamental trade-off between latency guarantees and average-case performance, we introduce the Duetto reference model. Duetto pairs a conventional memory arbiter with a real-time one. Most of the time, the memory resource is not overloaded, and Duetto can select the conventional arbiter providing high average performance. However, in the rare cases where latency guarantees risk being violated, Duetto is able to switch to the real-time controller, ensuring that the system is kept in a safe state.

Timing Analysis for Modern Multicore Platforms

By definition, the correctness of a real-time system depends on its ability to meet timing constraints (deadlines). Traditional real-time theory relies on the assumption of a known and constant Worst-Case Execution Time (WCET) for software tasks, but this assumption breaks down on complex modern processor architectures.

My group's research in this area is focused on the development of compositional analysis algorithms that allow the system designer to analyze each resource in isolation. In particular, my group has spearheaded the development of analysis techniques to compute worst-case delay bounds for access to main memory. An additional, significant body of work is targeted at the analysis of I/O traffic delay.

Single Core Equivalent Execution on Multicore Systems

While multicore architectures are nowadays widely employed in both general purpose and embedded systems, migrating safety-critical systems such as those in the avionics domain to multicore platforms has proven exceedingly difficult: the large number of architectural components shared among cores, such as caches, make verification and certification activities significantly more challenging compared to the single-core case. From an industrial perspective, integration, verification and certification costs can account for over 80% of total development expenses in safety-critical systems. To address this issue, my group has developed a large body of work targeted at predictable sharing of memory resources such as caches, scratchpads, and main memory.

The overall goal is Single Core Equivalent (SCE) execution: the execution of a SCE partition on a multicore is certifiably equivalent to the execution of the same partition on a single core system. Once we achieve this goal, large numbers of existing certified software developed for single core systems can be reused with standard single core (re)certification processes, a monumental saving in engineering and certification effort.

Network-on-Chip Design for Real-Time Embedded Systems

The increasing requirement for communication bandwidth in SoC platforms is driving the adoption of Networks-on-Chip as the interconnection of choice. In this project, we study the design of soft-NoCs on FPGA. We find that existing designs focus on preventing livelock but do not necessarily provide fair arbitration to nodes. This makes it difficult to integrate such designs in safety-critical embedded platforms requiring timing guarantees. To this end, we study how to re-engineer existing NoC design to provide predictable arbitration with provable latency bounds for packet transmission.