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Projects

Current Projects

Time-Predictable Resource Sharing for Commercial-Off-The-Shelf Embedded Architectures

Embedded systems are moving from federated architectures, where logical applications and subsystems are implemented on different hardware components, to progressively more integrated platforms which use extensive sharing of physical resources such as CPU time, memories, and power. Furthermore, they are increasingly built using Commercial-Off-The-Shelf (COTS) components in an attempt to increase performance and reduce cost and time to market. However, integrating COTS in safety-critical systems such as those in the medical, avionics and automotive industry is challenging. These systems require strict timing guarantees and isolation between subsystems to safely interact with the environment, but COTS are not typically designed with such objectives in mind.

PREM Scheduling IntervalThe main goal of this research is to prove that safe embedded systems can be built from high performance, inexpensive COTS components. In particular, in this project we will develop a methodology, called the PRedictable Execution Model (PREM), that greatly increases the time predictability of the memory and communication subsystems in COTS-based embedded hardware architectures. Under PREM, each task's execution is divided into a sequence of predictable intervals. Based on programmer's annotations, a specialized compiler modifies the code of each predictable interval to prefetch all required data at the beginning of the interval itself. After the prefetching is complete, the task can then execute without suffering any cache miss. Combining PREM with a suitable system-level co-scheduler for both CPU execution and peripheral traffic allows us to eliminate unpredictable contention for access to memory elements. Experiments on a single-core system show that PREM can reduce task's worst-case execution time as much as 60%. Since memory pressure increases more and more as additional cores are added to the system, we expects performance improvements to be even more significant in many-core systems.

Single Core Equivalent Execution of Avionic Partitions on Multicore Systems

Aircraft CommunicationIn this research project, we investigate the use of multicore architectures in safety-critical systems. In particular, we study the use of Integrated Modular Avionic (IMA) applications in such systems from the perspective of supporting safety certification. The multicore processor is different from its single core relatives in that concurrently executing cores share multiple physical resources such as caches, buses, chip interconnect networks, etc. Interdependences between shared resources create non-trivial timing anomalies that can significantly and unpredictably slow down execution. This is particularly dangerous because timing anomalies are difficult to isolate: resource accesses performed by a low-criticality partition can increase the execution time of tasks in a higher criticality partition. The main parameters that drive our research initiative are:

Avionic Display

  1. Backward compatibility,
  2. Certifiability for Safety,
  3. Worst-case analysis, and
  4. Isolation technology to bound cross-partition interference.

Our goal is to create the technology for Single Core Equivalent (SCE) IMA partitions. The key idea is that the execution of a SCE partition on a multicore is certifiably equivalent to the execution of the same partition on a single core system. Once we achieve this goal, large numbers of existing certified software developed for single core systems can be reused with standard single core (re)certification processes, a monumental saving in engineering and certification effort.


Previous Projects

Monitor and Control: Towards Dependable COTS-based Real-Time Embedded Systems

In modern computer architectures, COTS peripherals can autonomously initiate data transfers and contend for shared memory access. This can easily lead to violation of the temporal and functional isolation guaranteed at the CPU level. To guarantee dependable and predictable behavior for the next generation of COTS-based embedded systems, the following research tasks are pursued:

  1. We develop an innovative analysis framework that computes upper bounds to the timing interference imposed by peripherals on CPU tasks. The analysis can handle a variety of arbitration schemes, task models and cache architectures.
  2. We introduce the novel idea of a real-time bridge, implemented using a FPGA-based full system-on-chip (SoC). A real-time bridge separates a group of peripherals from the rest of the system controlling peripheral access to system resources.
  3. We employ run-time monitoring to check the behavior of untrusted components against their assumed specifications. If violations are detected, then an appropriate recovery measure is taken. Specifications are automatically synthesized into low-level monitors using the MOP framework.

Hybrid Hardware-Software Architecture for Reconfigurable Real-Time Systems

Modern SoC devices enable the development of hybrid embedded systems where sofware tasks, running on a traditional CPU, can coexist with hardware tasks running on reconfigurable hardware (FPGA). The main goal of this research is to develop a SoC real-time computing architecture that integrates hardware and software execution in a transparent manner, and supports QoS adaptation by means of partional reconfiguration of modern FPGA devices. Strong isolation guarantees are provided by monitoring the behavior of unpredictable IPs at run-time. A design methodology based on AADL has been developed and tested on the case study of a medical pacemaker.

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Real Time Ad-Hoc Wireless Communication Based on RT-Chains

In this work we designed and developed Real-Time Chains, a new prioritized MAC protocol to support soft real-time data flows in multi-hop wireless ad-hoc networks. RT-Chain avoids all packet collisions and limits the effect of priority inversions. Furthermore, it enables high spatial reuse and transmission rate using multiple wireless channels. We fully implemented and validated the protocol on MICAz hardware.

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