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Information for Prospective Students

Last Updated: August 2011. Note that thesis and project lists are subject to change without notice.

Undergraduate Students

Are you an outstanding undergraduate student looking to see what research is all about? Or perhaps are you thinking about graduate studies? There are two main ways you can be involved in my group.

  • ECE 499: this is the suggested way for 4th year students. ECE 499 can be taken as an elective course in either the 4A or 4B term. It consists of a research project supervised by an ECE faculty member. I am always looking for excellent students with a good average and an interest in either the 20s (computer architecture) or 50s (computer software) areas. If you are interested in taking ECE 499 with me in the upcoming semester, please send me an email with ECE499 in the title, a description of your interests and a brief academic record.
  • Undergraduate Research Assistantship (URA): I sometimes offer URAs based on needs. An URA requires you to work six hours per week on a specific project. It does not count towards your academic requirements, but you get paid. This opportunity is more suitable to second and third year students willing to work on a more scope-limited project. The list of available projects is subject to change and I do not offer URAs every term, so if you are interested your best option is to contact me directly. Please note that only students with 80%+ average are eligible, and make sure that you can commit to an extra six hours of work every week before applying.

These are some ideas for possible ECE 499 projects:

  • Hack the Linux kernel to implement some new and exciting research idea.
  • Build a Cyber-Physical simulator by connecting together two or more architecture simulators (ex: SIMICS) and/or dynamic system simulators (ex: Simulink)
  • Build a Cyber-Physical testbed to show the effectiveness of some of our research solutions (ex: a 3D helicopter controlled through cameras).

I am currently offering URA based on the two following projects. If you interested, please send me an email with "URA - Fall 2011" in the title.

  • Application parallelization for predictable multicore embedded systems: this project looks at running parallel embedded applications on multicore processors using the PRedictable Execution Model (PREM). In particular, the student will be responsible for taking a well-known benchmark application, parallelizing it and porting it to PREM. A state-of-the-art analysis and mapping methodology will be used to optimize the application execution for worst-case on an 8-core system. The student should be comfortable coding applications in a POSIX environment (more specifically, Linux).
  • Hardware support for OS-level driver memory management: memory management and memory operations are a major source of overhead and unpredictability in modern operating systems. For example, in most operating systems using protection levels, the OS must copy driver data from kernel-level structures to user-level stack before a process can use the input/output data. In the case of high-throughput peripherals such as 10Gigabit Network Cards, such copy can consume significant processor power, and interfere with other concurrent memory operations. The goal of this project is to build a DMA engine that can be used to perform the required memory copy in hardware. The DMA engine should be high-performance, as well as predictable and schedulable, i.e. the DMA operation should be coordinated with data transfers performed by other peripherals in the system. The student will be mainly responsible for implementing the DMA engine on a FPGA device using his choice of VHDL/Verilog. No previous knowledge of operating systems (ex: ECE254/354) is required, albeit you should be comfortable compiling and running programs on Linux.

Graduate Students

My group has openings both at the MASc and PhD level, to perform research on hardware/software architectures for the next generation of embedded systems (cyber-physical systems). I am looking for students with an interest in one or more of the following broad areas:

  • Operating Systems
  • Computer Architecture
  • Performance and Timing Analysis
  • Real-Time Scheduling and Resource Management

If you plan to apply to ECE at U Waterloo and you would like to work in my group, you are encouraged to contact me by email. Point out why you are interested in my research and why you think you would be a good addition to the team. If I like your background, I will usually ask you for a phone/skype interview.

Please note that admission to U Waterloo is highly competitive. I can not positively answer all requests. Past research experience in my core areas is not required for MASc students (however, expertise based on university courses and projects certainly helps), but it is a requirement when seeking direct admission in the PhD program. Many students in the department are first admitted in the MASc program and then move to the PhD program with the agreement of their advisor.

The following are some ideas for the type of Master/PhD thesis that you would be likely undertaking in my group; note that I strongly encourage independent and original research by all students.

Real-Time OS for Systems-on-Chip

By integrating all system components on a single die, the System-on-Chip (SoC) paradigm promises to greatly increase reliability and reduce costs, packaging size and power consumption of embedded systems. The explosion of the smart-phone market is a prime testament to such trend, but SoCs are also becoming more and more popular in real-time systems such as those employed in the avionic, automotive and medical industry.

Unfortunately, current real-time Operating Systems (OSs) are ill-suited to modern SoC architectures, because they rely on a critical assumption: the CPU is the only active component in the system. However, SoCs typically contain a variety of different processors, such as GPU, packet processors, compressors, etc., all of which are active components able to initiate communication and access memory. Hence, traditional CPU-based protection and isolation mechanisms are not sufficient anymore.

The goal of this thesis would be to design new OS abstraction and mechanisms to support strict isolation and timing predictability for applications running on multiple, heterogeneous processors on a SoC. Possible research topics include: 1) memory and cache partitioning; 2) task execution model; 3) driver model; 4) allocation of services; 5) virtualization and memory protection. Key objectives would be predictable performance, and ease of certification for safety-critical applications.

Timing Analysis for Complex Integrated Architectures

Modern Cyber-Physical Systems (CPS) are complex, integrated architectures. Timing analysis is crucial to ensure that the computation performed in the cyber part of the system (electronic components) correctly interacts with the physical world. Unfortunately, such analysis is made more complex by the presence of multiple cyber and physical resources shared both among hardware components and software applications. Such shared resources include processing cycles, interconnection bandwidth, cache space, memory bandwidth, power consumption and many more.

Traditionally, real-time timing analysis is performed by computing the worst-case interaction among all system components. Unfortunately, due to the number of shared resources, traditional worst-case analysis can prove incredibly pessimistic. Hence, the designer is often forced between the choice of over provisioning the cyber system based on worst case bounds, greatly increasing costs and power consumption, or sizing it based on average-case measures, which can sometimes lead to catastrophic occurrences.

The goal of this thesis would be to design new timing analysis that are less pessimistic than the current state-of-the-art, but still provides safe upper-bounds on resource usage. The key idea is that many worst-case scenarios can be avoiding through a careful assignment of shared resources. For example, CPU scheduling could be altered to avoid that two memory-intensive tasks run at the same time on a multi-core. Finally, statistical analysis can be applied to build confidence thresholds for interactions where the worst-case scenario is extremely unlikely to happen.

Application-Aware Architectures for Networks-on-Chip and Memory Hierarchies

Multi-core systems and SoC architectures require increasing communication bandwidth. The Network-on-Chip (NoC) paradigm, coupled with multi-level memory hierarchies and multiple memory controllers, is becoming a common solution to satisfy such needs.

Most of the research in the NoC domain have address the requirement of very flexible traffic allocation at run-time. However, not all application domains require such flexibility. For example, in Cyber-Physical Systems (CPS), the set of applications running on the system is typically well-known offline, together with their operational modes and resource requirements.

The key intuition in this research is that knowledge of the application behavior can be exploited to optimize NoC operations at run-time. It is likely that to take advantage of this opportunity, new NoC design paradigms and hardware-software co-design methodologies should be devised. Ideally, we would like to produce a set of standards that the industry could embrace to produce new SoC devices for the CPS market.