Research
[
Analog and Mixed Signal Circuits
|
Embedded Memories
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Digital Circuits
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VLSI Reliability and Testability
]
Thrust Areas:
- Primarily driven by high-performance and low-power arithmetic circuits (adders, register files, ALU)
- Energy delay optimized, robust, wide domino logic gates
- Dual supply clock grid designs / level converting circuits
- Implementation of timing diagnostics in multi-GHz ALUs
- Active power reduction using innovative logic styles and clocking strategies
- Dynamic voltage scaling architectures for portable applications
- Leakage power reduction using different techniques including reverse body bias (RBB) and their effectiveness with technology scaling
- Thermal issues in high performance circuits
- Estimation of on-chip temperature and process variation
Accomplishments:
- Designed and taped-out a 32-bit reduced swing adder
- Designed and taped-out a low power leakage tolerant 32x32 register file with split decoder scheme
- Designed and taped-out a dual supply CPL based 32-bit ALU with built-in delay diagnostics
- Designed and tape-out a 16x16 bit multiplier with a novel architecture to recover safety margin required by dynamic voltage scaling (DVS) and a critical path emulator to track the clitical path closely.