Research
[
Analog and Mixed Signal Circuits
|
Embedded Memories
|
Digital Circuits
|
VLSI Reliability and Testability
]
Thrust Areas:
- Primarily driven by embedded SRAM and content addressable memory (CAM)
- Low power SRAM design, test and reliability issues
- Soft error tolerant low power SRAM circuits and architectures
- Fault models for weak SRAM cells, programmable DFT techniques for detecting weak cells
- Low power high performance ternary CAM (TCAM) circuits and architectures
- Low power priority encoding circuits for CAMs including multiple match resolution
- Design for testability (DFT) of TCAMs and testing strategies for TCAMs
Accomplishments:
- Designed and taped-out an SRAM chip containing a low-power 64kb array with area efficient ECC, a 32kb array with soft error "immune cells", and two arrays with novel 4T cells.
- Designed and taped-out a 20Kb TCAM chip with priority encoder and testing circuitry. Chip contains a novel priority encoder, and three novel matchline sensing schemes.
- Designed a novel TCAM cell for low-energy and high-performance operation
- Designed and taped-out a novel high-performance and low-energy matchline sensing scheme for 144-bit word TCAMs
- Designed and taped-out a 256-bit priority encoder for CAMs using pulse-latched clocking and delayed-clock domino logic
- Designed and taped out an asynchronous SRAM test chip with a novel DFT technique for detecting weak cells in embedded SRAMs with digitally programmable detection threshold. Silicon measurement results proved the effectiveness of the proposed technique.
- Designed and taped out an 8Kb synchronous SRAM test chip with new DFT circuitry for stability faults detection with extended fault coverage, digital programmability of the detection threshold and short test time.
- Designed and taped out a 32kB SRAM cell array of novel low leakage power cells, a low read/write power SRAM cell and test circuitry