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Course Overview

Links and Dates

This Week's Schedule

Mon 8:30 Fri 8:30 Fri 12:30
Lecture Lecture Lecture Tutorial Lab Activity Deadlines Reading
wk-03 Jan 15-21 VHDL; Design Lec-06: State machines (CN:4.1) Lec-07: LeBlanc; Parcels; Bubbles (CN:4.2--4.4) Lec-08: RTL Simulation (CN:1.7)
Asn-02: Synthesis; FPGA cells (P1.8, P1.9, P3.2, P3.3)
Lab-2: State machines and datapaths
Lab-1 due Sun Jan 22 10:00pm


Instructor Mark Aagaard EIT-4138
Lab Instructor Eric Praetzel E2-2357
by request
TA Nusa Zidaric
TA Ahmed Ayoub

Times and Places

Mon Tue Wed Thur Fri
8:30 - 9:50
8:30 - 9:50
Lec (odd weeks)
12:30 - 1:20
Lab 1
E2 2364
1:30 - 2:50
Praetzel, Ayoub
Lab 2
E2 2364
1:30 - 2:50
Praetzel, Ayoub
Lab 3
E2 2364
1:30 - 2:50
Praetzel, Ayoub
4:30 - 5:20


The standard division of marks is:

Lab-1 1%
Lab-2 2%
Lab-3 3%
Project 24%
Midterm 20%
Final Exam 50%

There are two factors that cause the weights of the marks to be adjusted:

  1. If the final-exam mark is better than the midterm mark, then the weight of the final exam is increased and the weight of the midterm is decreased. The final exam weight can increase from 50% up to a maximum of 60%. The midterm weight can decrease from 20% down to a minimum of 10%. Thus, the combined weight of the midterm and final exam is always 70%. The measure of whether the final exam mark is "better" than the midterm mark is with respect to the average difference between the marks on the final and midterm.
  2. If the weighted average of the midterm mark and final exam mark is less than 60, then the combined weight of the exams increases linearily from 70% up to 100% for a combined exam mark of 50 or less.

The principles behind the rules for adjusting the weighting are:

  1. The marking scheme should be stable, in that a small change to the inputs (raw marks) should cause only a small change to the output (grade in the course).
  2. The grade in the course should reflect overall knowledge of the course material.
  3. If a student does poorly on the midterm and does well on the final exam, the final exam is more reflective of the student's overall knowledge of the course. This is the justification of adjusting the weight between the midterm and final. The minimum weight of the midterm is 10%, because the final exam is unable to cover all of the material in the course.
  4. The exams reflect the individual work of a student. If a student's exam mark indicates a failing mastery of the course material, then the student should fail the course. Thus a combined average of less than 50 for the midterm and final results in a course grade of less than 50.

Calendar Description

Design and modelling of digital systems using hardware description languages. Digital system design process. Impact of various implementation technologies. Design for testability. Fault tolerant systems. High performance systems. Project
Prereq: ECE 222, 223 and (3B Comp. Eng. or higher than 3B Elect. Eng.)

Notes, Textbook, etc

Course notes and lecture slides
The course notes and lecture slides will be the primary source of reading material for the course. They will be available on the web under Course Material.
Piazza Q&A Forum
The Piazza ece327 discussion forum is the primary forum for announcements, questions and answers. You are encouraged to read it regularly, and to respond to other students' questions if you have some helpful information.


The tutorials will cover problems from the Problems and Solutions documents. The first document contains problem statements and the second contains solutions. The problems come from previous midterm and final exams, and so are a good indication of the material that will be tested on the exam. The specific problems that will be covered each week are listed on the schedule.

Computer and Lab Facilities

The course will use synthesis software from Mentor Graphics (Precision RTL) and Altera (Quartus) and simulation software from Mentor Graphics (ModelSim).


There are three labs to introduce you to VHDL, the simulation software, the synthesis software, and the FPGAs that we will be using. The third lab is a design challenge/opportunity, and so is more difficult than than the first two labs.

Lab 1 Adders and flip-flops
Lab 2 State machines and datapaths
Lab 3 Preview of the project

You may work individually or in groups of two for the labs.


The project will be the design of a variation of a Kirsch edge-detector circuit in VHDL. The project shall be done in groups four. Marking will be based on area/performance, correct functionality, a demo, and a brief report.


Final Exam

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