Highly Qualified Personnel (HQP) under my direct supervisions are marked
with *
Referred journal publications with major contributions
X. Chen*, S. Boumaiza, L. Wei, “Modeling Self-Heating in GaN HEMTs using Two Heat Sources,” submitted to IEEE Electron Device Letters (EDL), 2019.
X. Chen*, S. Boumaiza, L. Wei, “Self-Heating and Equivalent Channel Temperature in Short Gate Length GaN HEMTs,” accepted by IEEE Transactions on Electron Devices (TED). 2019.
Z. Yang*, S. Zarabi*, E. Fernandes*, I. Rua, H. Debeda, A. Salehian, D. Nairn, L. Wei, “A Simple Wireless Sensor Node System for Electricity Monitoring Applications: Design, Integration, and Testing with Different Piezoelectric Energy Harvesters,” Sensors. No. 11, 2018.
E. Fernandes*, M. Blake, I. Rue, S. Zarabi*, H. Debeda, D. Nairn, L. Wei, A. Salehian, “Design, Fabrication, and Testing of a Low Frequency MEMS Piezoelectromagnetic Energy Harvester,” p.1 – 16, Smart Materials and Structures (SMS), vol. 27, No. 3, 2018
A. Tosson*, S. Yu, M. Anis and L. Wei, “Proposing a Solution for Single-Event Upset in 1T1R RRAM Memory Arrays,” IEEE Transaction on Nuclear Science (TNS), vol. 65, No. 6, pp 1239-1247, Jun. 2018
A. Tosson*, S. Yu, M. Anis, and L. Wei, “A Study of
the Effect of RRAM Reliability Soft Errors on the Performance of RRAM-based
Neuromorphic Systems,” IEEE Transactions on Very Large Scale Integration (TVLSI), Vo. 25, No. 11, pp 3125-3137, Nov. 2017
H. Zhang*, M. Gupta, J. Watt and L. Wei, "Effective
Drive Current for Pass-Gate Transistors," in IEEE Transactions on Electron Devices (TED), vol. 63, no. 8, pp. 2999-3004, Aug. 2016.
K. Sheikh*, S-J. Han, and Lan Wei, "CNFET With Process
Imperfection: Impact on Circuit-Level Yield and Device Optimization," IEEE Transactions on Circuits and Systems I: Regular Papers, (TCAS-I) vol. 63, no. 12, pp. 2209-2221, 2016.
J. Luo, L. Wei, C.-S. Lee, A. D. Franklin, X. Guan,
E. Pop, D. A. Antoniadis, H.-S. P. Wong, “A Compact Model for Carbon
Nanotube Field-Effect Transistors Including Non-Idealities and Calibrated
with Experimental Data Down to 9 nm Gate Length ,” IEEE Transactions on Electron Devices(TED), vol. 60, No 6, pp. 1834 – 1843 ,
2013.
L. Wei, O. Mysore, D. A. Antoniadis, "Virtual-Source-Based
Self-Consistent Current and Charge FET Models: From Ballistic to
Drift-Diffusion Velocity-Saturation Operation,"IEEE Transactions on Electron Devices (TED), vol.59, no.5, pp.1263-1271, May 2012.
L. Wei, D. Frank, L. Chang, and H.-S. P. Wong,
“Non-iterative Compact Model for Intrinsic Carbon Nanotube FETs: Quantum
Capacitances and Transport,” IEEE Transactions on Nanotechnology(TNANO), vol. 58, No. 8, pp.
2456-2465, 2011.
L. Wei, S. Oh, H. –S. P. Wong, “Technology Assessment
Methodology for Complementary Logic Applications based on Energy-Delay
Optimization,” IEEE Transactions on Electron Devices(TED), vol. 58, No. 8, pp. 2430-2439,
2011.
L. Wei, F. Boeuf, T. Skotnicki, and H.-S. P. Wong, “Parasitic
Capacitances: Analytical Models and Impact on Circuit-Level Performance,”IEEE Transactions on Electron Devices(TED), vol. 58, No. 5, pp. 1361-1370,
2011.
L. Wei, J. Deng, L.-W. Chang, K. Kim, C.-T. Chuang, and H. -S.
P. Wong, "Selective Device Structure Scaling and Parasitics Engineering: A
Way to Extend the Technology Roadmap,"IEEE Transactions on Electron Devices(TED), vol. 56, No.2, pp. 312 – 320,
February, 2009.
L. Wei, J. Deng, and H.-S. P. Wong, “Modeling and Performance
Comparison of 1-D and 2-D Devices Including Parasitic Gate Capacitance and
Screening Effect,” IEEE Transactions on Nanotechnology(TNANO), vol. 7, No. 6, pp. 720 – 727,
November, 2008.
Referred conference publications with major contributions
Z. Yang*, Y. Ma*, L. Wei, “Functionally Complete Boolean Logic and Adder Design Based on 2T2R RRAMs for Post-CMOS In-Memory Computing,” IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI2019), Washington, DC, USA, May 2019
Z. Yang*, L. Wei, “Logic Circuit and Memory Design for In-Memory Computing Applications Using Bipolar RRAMs,” 2019 IEEE International Symposium on Circuits and Systems (ISCAS2019), Sapporo, Japan, May 2019
H. Elgabra*, B. Buonacorsi, C. Chen, J. Watt, J. Baugh, L. Wei, “Virtual Source based I-V Model for Cryogenic CMOS Devices,” the 2019 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA2019), Hsinchu, Taiwan, Apr 2019
K. Sheikh*, L. Wei, “Methodology to Generate Approximate Circuits to Reduce Process Induced Degradation in CNFET Based Circuits,” International Conference on Simulation of Semiconductor Processes and Devices 2018 (SISPAD2018), Austin, USA, 2018.
Z. Yang*, S. Zarabi*, E. Fernandes*, I. Rua, H. Debeda, A. Salehian, D. Nairn, L. Wei, “Electricity Monitoring System with Interchangeable Piezoelectric Energy Harvesters and Dynamic Power Management Circuitry,” the 18th IEEE International conference on Nanotechnology (IEEE NANO 2018), Cork, Ireland, Jul. 2018
K. Sheikh*, L. Wei, “Methodology to Capture Statistical Effect of Process Imperfections on Glitch Suppression in CNFET circuits and Counter using Approximate Circuits,” IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI2018), Chicago, USA, May 2019
K. Sheikh*, L. Wei, “Evaluation of Circuit Performance Degradation due to CNT Process Imperfection,” the 2018 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA2018), Hsinchu, Taiwan, Apr 2018
K. Sheikh*, L. Wei, “Using Approximate Circuits to Counter Process Imperfections in CNFET based Circuits,” the 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT2018), Hsinchu, Taiwan, Apr 2018
H. Zhang*, A. Raslan, S. Boumaiza, L. Wei, “Physics
based Compact Model of GaN HEMT with an Efficient Parameter Extraction
Flow,” paper 1118, 2017 IEEE 12th International Conference on ASIC
(ASICON2017).
S. Zarabi*, E. Fernandes*, I. Rua, H. Debeda, C.
Lucat, A. Salehian, D. Narin, and L. Wei, “Design and Development of
a Self-contained Integrated System for Electricity Monitoring
Applications,” paper 1024,2017 IEEE 12th International Conference on ASIC (ASICON2017)
A. Tosson*, S. Yu, M. Anis, L. Wei,
"Impact of the RRAM Reliability Failures on the Performance of the
RRAM-based Neuromorphic Systems", 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI2017), July 2017.
A.Tosson*, S. Yu, M. Anis, L. Wei,
"Mitigating the Effect of the Reliability Soft-errors of the RRAM Devices
on the Performance of the RRAM-based Neuromorphic Systems", IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI2017), pp. 53 –
58, May. 2017.
E. Fernandes*, S. Zarabi*, H. Debéda, C. Lucat,
D. Nairn, L. Wei and A. Salehian, “ Modelling and
fabrication of a compliant centrally supported meandering piezoelectric
energy harvester using screen-printing technology,”PowerMEMS2016; Journal of Physics: Conference Series (JPCS) vol. 773, 012109.
A.Tosson*, M. Anis, and L. Wei, "RRAM
Refresh Circuit: A Proposed Solution To Resolve The Soft-Error Failures For
HfO2/Hf 1T1R RRAM Memory Cell",IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI2016), pp. 227 –
232, May. 2016
A. Tosson*, A. Neale, M. Anis, L. Wei,
“8T1R: A Novel Low-power High-speed RRAM-based Non-volatile SRAM Design,”IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI2016), pp. 239 –
244, May. 2016
K. Sheikh*, S-J.Han, and L. Wei, "Impact of CNT
process imperfection on circuit-level functionality and yield," in2016 IEEE International Symposium onCircuits and Systems (ISCAS2016), pp. 401-404, May 2016. (Invited paper)
U. Radhakrishna, L. Wei, D.-S. Lee, T. Palacios, D. A.
Antoniadis, “Physics-based GaN HEMT Transport and Charge Model:
Experimental Verification and Performance Projection,”2012 IEEE International Electron Devices Meeting (IEDM2012), paper 13.6, Dec, 2012.
L. Wei and D. A. Antoniadis, “CMOS Device Design and
Optimization from a Perspective of Circuit-Level Energy-Delay
Optimization,”
2011 IEEE International Electron Devices Meeting (IEDM2011)
, paper 15.3, Washington D.C., USA, December 5– 7, 2011.
J. T. Ryan, L. Wei, J. P Campbell, R. G. Southwick, K. P.
Cheung, A. S. Oates, H. –S. P. Wong, and J. Suehle, “When Does a Circuit
Really Fail?”,
2011 IEEE International Integrated Reliability Workshop (IRW2011)
, paper 3.2, South Lake Tahoe, USA, October 16– 20, 2011.
J. T. Ryan, L. Wei, J. P Campbell, R. G. Southwick, K. P.
Cheung, A. S. Oates, H. –S. P. Wong, and J. Suehle, “Circuit-Aware Device
Reliability Criteria Methodology,”
the 41th European Solid-State Device Research Conference (ESSDERC2011)
, pp. 255– 258, Helsinki, Finland, September 12– 16, 2011.
L. Wei, H. –S. P. Wong, “A Fully Analytical Compact Model for
Carbon Nanotube Field Effect Transistors including Quantum Capacitances and
Electrostatic Model,” 2011 Workshop on Compact Modeling (WCM2011), pp.
738-741, Boston, USA, Jun 13—16, 2011. (Invited paper)
L. Wei, S. Oh, and H. –S. Philip Wong, “Performance Benchmarks
for Si, III-V, TFET, and carbon nanotube FET – Re-thinking the Technology
Assessment Methodology for Complementary Logic Applications,”
2010 IEEE International Electron Devices Meeting (IEDM2010)
, paper 16.2, San Francisco, USA, December 6 – 8, 2010.
S. Oh, L. Wei, S. Chong, J. Luo, and H.-S. P. Wong, “Device and
Circuit Interactive Design and Optimization Beyond the Conventional Scaling
Era,” in
2010 IEEE International Electron Devices Meeting (IEDM2010)
, San Francisco, USA, December 6 – 8, 2010. (Invited paper
)
J. Luo, L. Wei, F. Boeuf, D. Antoniadis, T. Skotnicki, and
H.-S. P. Wong, “Device Engineering for Improving SRAM Static Noise
Margin,”
2010 International Conference on Solid State Devices and Materials
(SSDM2010),
paper C-4-3, Tokyo, Japan, September 22 – 24, 2010.
L. Wei, D. Frank, L. Chang, and H.-S. P. Wong, “A Non-iterative
Compact Model for Carbon Nanotube FETs Incorporating Source Exhaustion
Effects,”
2009 IEEE International Electron Devices Meeting (IEDM2009),
pp. 917 – 920, Baltimore, USA, December 6 – 9, 2009.
L. Wei, F. Boeuf, D. Antoniadis, T. Skotnicki, and H.-S. P.
Wong, “Exploration of Device Design Space to Meet Circuit Speed Targeting
22nm and Beyond,”
2009 International Conference on Solid State Devices and Materials (SSDM2009),
pp. 808 – 809, Sendai, Japan,September 23 – 26, 2009.
H.-S. P. Wong, L. Wei, S. Oh, A. Lin, J. Deng, S. Chong, and K.
Akarvardar, “Technology Projection Using Simple Compact Models,”
2009 International Conference on Simulation of Semiconductor Processes
and Devices (SISPAD2009),
pp. 1 – 8, San Diego, USA, September 9 – 11, 2009. (Invited plenary paper)
L. Wei
, F. Boeuf, T. Skotnicki, and H.-S. P. Wong, “CMOS Technology Roadmap
Projection Including Parasitic Effects,”
2009 International Symposium on VLSI Technology, Systems and
Applications (VLSI-TSA2009)
, pp. 78 – 79, Hsinchu, Taiwan, April 27 – 29, 2009.
H.-S. P. Wong, L. Wei, and J. Deng, “The Future of CMOS
Scaling – Parasitics Engineering and Device Footprint Scaling,” invited
paper,
2008 International Conference on Solid State and Integrated Circuit
Technology (ICSICT2008),
pp. 21 – 24, Beijing, China, October 20 – 23, 2008.
L. Wei, D. Frank, L. Chang, H.-S. P. Wong, “An Analytical Model
for Intrinsic Carbon Nanotube FETs,”
the 38th European Solid-State Device Research Conference (ESSDERC2008),
pp.222 – 225, Edinburgh, United Kingdom, September 15 – 19, 2008.
J. Deng, L. Wei, L.-W. Chang, K. Kim, C.-T. Chuang, and H.-S. P.
Wong, "Extending Technology Roadmap by Selective Device Footprint Scaling
and Parasitics Engineering," 2008
International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA2008),
pp. 159 – 160, Hsinchu, Taiwan, April 21 – 23, 2008.
L. Wei, J. Deng, and H.-S. P. Wong, “1-D and 2-D Devices
Performance Comparison including Parasitic Gate Capacitance and Screening
Effect,”
2007 IEEE International Electron Devices Meeting (IEDM2007)
, pp. 741 – 744, Washington, D. C., USA, December 10 – 12, 2007.
L. Wei, J. Gao, L. Ji, Z. Chen “A New Structure of Low-Noise CMOS Differential
Amplifier”,
the 6th International Conference on ASIC (ASICON2005),
pp. 360 – 364, vol. 1, Shanghai, October 24 – 27, 2005.
Referred journal and conference publications with collaborative contributions
X. Jiang, J. Wang, X. Wang, R. Wang, B Cheng, A. Asenov, L. Wei,
and R. Huang, “New Assessment Methodology Based on Energy Delay Yield Co
optimization for Nanoscale CMOS Technology,”IEEE Transactions on Electron Devices (TED), vol. 62, no. 6, pp. 1746-1753, June 2015.
Z. Zhang, A. Lin, N. Patil, H. Wei, L. Wei, H.-S. P. Wong, and
S. Mitra, “Robust Digital VLSI using Carbon Nanotubes”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems
(TCAD), vol. 31, No. 4, pp. 453-471, 2012.
H. Debéda, I. Rua, E. Fernandes*, S. Zarabi*, D.
Nairn, L. Wei, and A. Salehian, “Printed MEMS-based Self-contained
Piezoelectric-based Monitoring Device for Smart Grids,” the 17th International Conference on Micro and Nanotechnology for Power Generation and Energy Conversion Applications (PowerMEMS2017), Kanasawa, Japan, Nov 2017.
I. Rua, H. Debéda, E. Fernandes*, S. Zarabi*, D.
Nairn, L. Wei, and A. Salehian, “ Optimization of the fabrication of a low
frequency energy harvester made of printed PZT layers on a meander shape
stainless substrate,”
2017 Conference on Design, Test, Integration and Packaging for
MEMS/MOEMS
(DTIP2017), May 2017.
L. Yu, O. Mysore, L. Wei, L. Daniel, D. Antoniadis, I. Elfade, D.
Boning, “An Ultra-Compact Virtual Source FET Model for Deeply-Scaled
Devices: Parameter Extraction and Validation for Standard Cell Libraries
and Digital Circuits,” 18th Asia and South Pacific Design Automation
Conference (ASPDAC 2013), pp.521-526, 2013
L. Yu, L. Wei, D. Antoniadis, I. Elfadel, D. Boning, “Statistical
Modeling with the Virtual Source MOSFET Model,” pp1454-1457, 2013 The
Design, Automation, and Test in Europe Conference (DATE 2013), 2013.
C. Sun, C.-H. Chen, G. Kurian, L. Wei, J. Miller, A. Agarwal,
L.-S. Peh and V. Stojanovic , “DSENT – A Tool Connecting Emerging Photonics
with Electronics for Opto-Electronic Networks-on-Chip Modeling,”
6th ACM/IEEE International Symposium on Networks-on-Chip (NOCS2012),
Lyngby, Denmark, May 9-11, 2012.
G. Kurian, C. Sun, C.-H. Chen, J. E. Miller, J. Michel, L.Wei,
D. A. Antoniadis, L.-S. Peh, L. Kimerling, Vladimir Stojanovic and Anant
Agarwal, “Cross-layer Energy and Performance Evaluation of a Nanophotonic
Manycore Processor System using Real Application Workloads,”
26th IEEE International Parallel & Distributed Processing Symposium
(IPDPS2012), pp. 1117-1130, 2012.
H. –S. P. Wong, S. Mitra, D. Akinwande, C. Beasley, Y. Chai, H. –Y.
Chen, X. Chen, G. Close, J. Deng, A. Hazeghi, J. Liang, A. Lin, L. S.
Liyanage, J. Luo, J. Parker, N. Patil, M. Shulaker, H. Wei, L. Wei,
J. Zhang, “Carbon Nanotube Electronics – Materials, Devices, Circuit,
Design, Modeling, and Performance Projection,”
IEEE International Electron Devices Meeting (IEDM 2011
)
.
H. Wei, J. Zhang, L. Wei, N. Patil, A. Lin, M.
Shulaker, H.-Y. Chen, H. -S. P. Wong and S. Mitra, “Carbon Nanotube
Imperfection-Immune Digital VLSI: Frequently Asked Questions Updated,”2011 International Conference on Computer-Aided Design (ICCAD2011), pp.
227-230, November 7-10, 2011.
X. Chen, A. Lin, L. Wei, N. Patil, H. Wei, H.-Y. Chen, S. Mitra,
and H.-S. P. Wong, “Carbon-Based Nanomaterial for Nanoelectronics”, the Electrochemical Society Trans. vol. 35, pp. 259-269, 2011.
H.-Y. Chen, N. Patil, A. Lin, L. Wei, Ca. Beasley, J. Zhang, X. Chen,
H. Wei, L. Liyanage, M. SHulaker, S. Mitra, H.-S. P. Wong, “Carbon
electronics- From material synthesis to circuit demonstration,” “CMOS
Technology Roadmap Projection Including Parasitic Effects,” 2011
International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA2011)
, pp. 1-2, Hsinchu, Taiwan, April 25 – 27, 2011.
Seminar and invited talks
L. Wei and K. Sheikh*, “Impact of Process Imperfection of CNFET on Circuit-level Performance and Proposal to Improve using Approximate Circuits”, 2018 International Conference on Solid-State and Integrated Circuit Technology (ICSICT2018) (Invited talk)
L. Wei and K. Sheikh*, “Using Approximate Circuit to Improve Process Induced Failure in CNFET Circuits,” The 6th Carbon Nanotube Thin Film Electronics and Applications Symposium (CNTFA18) (Invited talk)
A. Tosson*, S. Yu, M. Anis and L. Wei, “1T2R: A Novel
Memory Cell Design to Resolve Single-Event Upset in RRAM Arrays,” paper
918, 2017 IEEE 12th International Conference on ASIC (ASICON2017) (Invited paper)
L. Wei, “Technology Assessment based on Device and Circuit
Interaction and Optimization,” CMOS Emerging Technologies Research
, Vancouver, Canada, 2015 (Invited talk)
L. Wei, “Technology Assessment based on Device and Circuit
Interaction and Optimization, ” seminar at IEEE Montreal Circuits and
Systems Chapter, Montreal, Canada, Nov 2014 (Seminar)
L. Wei, “Nanoelectronics: Technology Assessment and Projection
at the Device, Circuit, and System Level.” (Seminar)
Stanford University, USA (Jan 2009), Johns Hopkins University, USA (Feb
2009), University of Southern California, USA (Mar 2009), University of
California San Diego, USA (Mar 2009), University of California Riverside,
USA (Mar 2009), Carnegie Mellon University, USA (Mar 2009), Shanghai
Jiaotong University, China (Apr 2009), University of California Berkeley,
USA (Apr 2009)
L. Wei, “Device and Circuit Interactive Design.” (Seminar)
Pennsylvania State University, USA (Nov 2011), Semiconductor
Manufacturing International Corporation, China, (Jan 2012), Chinese
University of Hong Kong, Hong Kong (Jan 2012), Altera Corporation, USA (Feb
2012), Cornell University, USA (Mar 2012), University of Toronto, Canada
(Apr 2012), IBM Semiconductor Research and Development Center, USA (May
2012), Qualcomm Research Center, USA (May 2012), University of Waterloo,
Canada (Jul 2012), University of Houston, USA (Aug 2012).
L. Wei and H.-S. Philip Wong, “Compact Modeling Aided Technology Design
and Projection Considering System-Level Performance,” 2009 MOS Modeling and
Parameter Extraction Working Group (MOS-AK/GSA), Baltimore, USA, Dec, 2009. (Invited talk)
Publications
Last updated Jun 2019
- X. Chen*, S. Boumaiza, L. Wei, “Modeling Self-Heating in GaN HEMTs using Two Heat Sources,” submitted to IEEE Electron Device Letters (EDL), 2019.
- X. Chen*, S. Boumaiza, L. Wei, “Self-Heating and Equivalent Channel Temperature in Short Gate Length GaN HEMTs,” accepted by IEEE Transactions on Electron Devices (TED). 2019.
- Z. Yang*, S. Zarabi*, E. Fernandes*, I. Rua, H. Debeda, A. Salehian, D. Nairn, L. Wei, “A Simple Wireless Sensor Node System for Electricity Monitoring Applications: Design, Integration, and Testing with Different Piezoelectric Energy Harvesters,” Sensors. No. 11, 2018.
- E. Fernandes*, M. Blake, I. Rue, S. Zarabi*, H. Debeda, D. Nairn, L. Wei, A. Salehian, “Design, Fabrication, and Testing of a Low Frequency MEMS Piezoelectromagnetic Energy Harvester,” p.1 – 16, Smart Materials and Structures (SMS), vol. 27, No. 3, 2018
- A. Tosson*, S. Yu, M. Anis and L. Wei, “Proposing a Solution for Single-Event Upset in 1T1R RRAM Memory Arrays,” IEEE Transaction on Nuclear Science (TNS), vol. 65, No. 6, pp 1239-1247, Jun. 2018
- A. Tosson*, S. Yu, M. Anis, and L. Wei, “A Study of
the Effect of RRAM Reliability Soft Errors on the Performance of RRAM-based
Neuromorphic Systems,” IEEE Transactions on Very Large Scale Integration (TVLSI), Vo. 25, No. 11, pp 3125-3137, Nov. 2017
- H. Zhang*, M. Gupta, J. Watt and L. Wei, "Effective
Drive Current for Pass-Gate Transistors," in IEEE Transactions on Electron Devices (TED), vol. 63, no. 8, pp. 2999-3004, Aug. 2016.
- K. Sheikh*, S-J. Han, and Lan Wei, "CNFET With Process
Imperfection: Impact on Circuit-Level Yield and Device Optimization," IEEE Transactions on Circuits and Systems I: Regular Papers, (TCAS-I) vol. 63, no. 12, pp. 2209-2221, 2016.
- J. Luo, L. Wei, C.-S. Lee, A. D. Franklin, X. Guan,
E. Pop, D. A. Antoniadis, H.-S. P. Wong, “A Compact Model for Carbon
Nanotube Field-Effect Transistors Including Non-Idealities and Calibrated
with Experimental Data Down to 9 nm Gate Length ,” IEEE Transactions on Electron Devices (TED), vol. 60, No 6, pp. 1834 – 1843 ,
2013 .
- L. Wei, O. Mysore, D. A. Antoniadis, "Virtual-Source-Based
Self-Consistent Current and Charge FET Models: From Ballistic to
Drift-Diffusion Velocity-Saturation Operation,"IEEE Transactions on Electron Devices (TED), vol.59, no.5, pp.1263-1271, May 2012.
- L. Wei, D. Frank, L. Chang, and H.-S. P. Wong,
“Non-iterative Compact Model for Intrinsic Carbon Nanotube FETs: Quantum
Capacitances and Transport,” IEEE Transactions on Nanotechnology (TNANO), vol. 58, No. 8, pp.
2456-2465, 2011.
- L. Wei, S. Oh, H. –S. P. Wong, “Technology Assessment
Methodology for Complementary Logic Applications based on Energy-Delay
Optimization,” IEEE Transactions on Electron Devices (TED), vol. 58, No. 8, pp. 2430-2439,
2011.
- L. Wei, F. Boeuf, T. Skotnicki, and H.-S. P. Wong, “Parasitic
Capacitances: Analytical Models and Impact on Circuit-Level Performance,”IEEE Transactions on Electron Devices (TED), vol. 58, No. 5, pp. 1361-1370,
2011.
- L. Wei, J. Deng, L.-W. Chang, K. Kim, C.-T. Chuang, and H. -S.
P. Wong, "Selective Device Structure Scaling and Parasitics Engineering: A
Way to Extend the Technology Roadmap,"IEEE Transactions on Electron Devices (TED), vol. 56, No.2, pp. 312 – 320,
February, 2009.
- L. Wei, J. Deng, and H.-S. P. Wong, “Modeling and Performance
Comparison of 1-D and 2-D Devices Including Parasitic Gate Capacitance and
Screening Effect,” IEEE Transactions on Nanotechnology (TNANO), vol. 7, No. 6, pp. 720 – 727,
November, 2008.
- Z. Yang*, Y. Ma*, L. Wei, “Functionally Complete Boolean Logic and Adder Design Based on 2T2R RRAMs for Post-CMOS In-Memory Computing,” IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI2019), Washington, DC, USA, May 2019
- Z. Yang*, L. Wei, “Logic Circuit and Memory Design for In-Memory Computing Applications Using Bipolar RRAMs,” 2019 IEEE International Symposium on Circuits and Systems (ISCAS2019), Sapporo, Japan, May 2019
- H. Elgabra*, B. Buonacorsi, C. Chen, J. Watt, J. Baugh, L. Wei, “Virtual Source based I-V Model for Cryogenic CMOS Devices,” the 2019 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA2019), Hsinchu, Taiwan, Apr 2019
- K. Sheikh*, L. Wei, “Methodology to Generate Approximate Circuits to Reduce Process Induced Degradation in CNFET Based Circuits,” International Conference on Simulation of Semiconductor Processes and Devices 2018 (SISPAD2018), Austin, USA, 2018.
- Z. Yang*, S. Zarabi*, E. Fernandes*, I. Rua, H. Debeda, A. Salehian, D. Nairn, L. Wei, “Electricity Monitoring System with Interchangeable Piezoelectric Energy Harvesters and Dynamic Power Management Circuitry,” the 18th IEEE International conference on Nanotechnology (IEEE NANO 2018), Cork, Ireland, Jul. 2018
- K. Sheikh*, L. Wei, “Methodology to Capture Statistical Effect of Process Imperfections on Glitch Suppression in CNFET circuits and Counter using Approximate Circuits,” IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI2018), Chicago, USA, May 2019
- K. Sheikh*, L. Wei, “Evaluation of Circuit Performance Degradation due to CNT Process Imperfection,” the 2018 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA2018), Hsinchu, Taiwan, Apr 2018
- K. Sheikh*, L. Wei, “Using Approximate Circuits to Counter Process Imperfections in CNFET based Circuits,” the 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT2018), Hsinchu, Taiwan, Apr 2018
- H. Zhang*, A. Raslan, S. Boumaiza, L. Wei, “Physics
based Compact Model of GaN HEMT with an Efficient Parameter Extraction
Flow,” paper 1118, 2017 IEEE 12th International Conference on ASIC
(ASICON2017).
- S. Zarabi*, E. Fernandes*, I. Rua, H. Debeda, C.
Lucat, A. Salehian, D. Narin, and L. Wei, “Design and Development of
a Self-contained Integrated System for Electricity Monitoring
Applications,” paper 1024,2017 IEEE 12th International Conference on ASIC (ASICON2017)
- A. Tosson*, S. Yu, M. Anis, L. Wei,
"Impact of the RRAM Reliability Failures on the Performance of the
RRAM-based Neuromorphic Systems", 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI2017), July 2017.
- A.Tosson*, S. Yu, M. Anis, L. Wei,
"Mitigating the Effect of the Reliability Soft-errors of the RRAM Devices
on the Performance of the RRAM-based Neuromorphic Systems", IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI2017), pp. 53 –
58, May. 2017.
- E. Fernandes*, S. Zarabi*, H. Debéda, C. Lucat,
D. Nairn, L. Wei and A. Salehian, “ Modelling and
fabrication of a compliant centrally supported meandering piezoelectric
energy harvester using screen-printing technology,”PowerMEMS2016; Journal of Physics: Conference Series (JPCS) vol. 773, 012109.
- A.Tosson*, M. Anis, and L. Wei, "RRAM
Refresh Circuit: A Proposed Solution To Resolve The Soft-Error Failures For
HfO2/Hf 1T1R RRAM Memory Cell",IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI2016), pp. 227 –
232, May. 2016
- A. Tosson*, A. Neale, M. Anis, L. Wei,
“8T1R: A Novel Low-power High-speed RRAM-based Non-volatile SRAM Design,”IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI2016), pp. 239 –
244, May. 2016
- K. Sheikh*, S-J.Han, and L. Wei, "Impact of CNT
process imperfection on circuit-level functionality and yield," in2016 IEEE International Symposium on Circuits and Systems (ISCAS2016), pp. 401-404, May 2016. (Invited paper)
- U. Radhakrishna, L. Wei, D.-S. Lee, T. Palacios, D. A.
Antoniadis, “Physics-based GaN HEMT Transport and Charge Model:
Experimental Verification and Performance Projection,”2012 IEEE International Electron Devices Meeting (IEDM2012), paper 13.6, Dec, 2012.
- L. Wei and D. A. Antoniadis, “CMOS Device Design and
Optimization from a Perspective of Circuit-Level Energy-Delay
Optimization,”
2011 IEEE International Electron Devices Meeting (IEDM2011)
, paper 15.3, Washington D.C., USA, December 5– 7, 2011.
- J. T. Ryan, L. Wei, J. P Campbell, R. G. Southwick, K. P.
Cheung, A. S. Oates, H. –S. P. Wong, and J. Suehle, “When Does a Circuit
Really Fail?”,
2011 IEEE International Integrated Reliability Workshop (IRW2011)
, paper 3.2, South Lake Tahoe, USA, October 16– 20, 2011.
- J. T. Ryan, L. Wei, J. P Campbell, R. G. Southwick, K. P.
Cheung, A. S. Oates, H. –S. P. Wong, and J. Suehle, “Circuit-Aware Device
Reliability Criteria Methodology,”
the 41th European Solid-State Device Research Conference (ESSDERC2011)
, pp. 255– 258, Helsinki, Finland, September 12– 16, 2011.
- L. Wei, H. –S. P. Wong, “A Fully Analytical Compact Model for
Carbon Nanotube Field Effect Transistors including Quantum Capacitances and
Electrostatic Model,” 2011 Workshop on Compact Modeling (WCM2011), pp.
738-741, Boston, USA, Jun 13—16, 2011. (Invited paper)
- L. Wei, S. Oh, and H. –S. Philip Wong, “Performance Benchmarks
for Si, III-V, TFET, and carbon nanotube FET – Re-thinking the Technology
Assessment Methodology for Complementary Logic Applications,”
2010 IEEE International Electron Devices Meeting (IEDM2010)
, paper 16.2, San Francisco, USA, December 6 – 8, 2010.
- S. Oh, L. Wei, S. Chong, J. Luo, and H.-S. P. Wong, “Device and
Circuit Interactive Design and Optimization Beyond the Conventional Scaling
Era,” in
2010 IEEE International Electron Devices Meeting (IEDM2010)
, San Francisco, USA, December 6 – 8, 2010. (Invited paper
)
- J. Luo, L. Wei, F. Boeuf, D. Antoniadis, T. Skotnicki, and
H.-S. P. Wong, “Device Engineering for Improving SRAM Static Noise
Margin,”
2010 International Conference on Solid State Devices and Materials
(SSDM2010),
paper C-4-3, Tokyo, Japan, September 22 – 24, 2010.
- L. Wei, D. Frank, L. Chang, and H.-S. P. Wong, “A Non-iterative
Compact Model for Carbon Nanotube FETs Incorporating Source Exhaustion
Effects,”
2009 IEEE International Electron Devices Meeting (IEDM2009),
pp. 917 – 920, Baltimore, USA, December 6 – 9, 2009.
- L. Wei, F. Boeuf, D. Antoniadis, T. Skotnicki, and H.-S. P.
Wong, “Exploration of Device Design Space to Meet Circuit Speed Targeting
22nm and Beyond,”
2009 International Conference on Solid State Devices and Materials (SSDM2009),
pp. 808 – 809, Sendai, Japan, September 23 – 26, 2009.
- H.-S. P. Wong, L. Wei, S. Oh, A. Lin, J. Deng, S. Chong, and K.
Akarvardar, “Technology Projection Using Simple Compact Models,”
2009 International Conference on Simulation of Semiconductor Processes
and Devices (SISPAD2009),
pp. 1 – 8, San Diego, USA, September 9 – 11, 2009. (Invited plenary paper)
- L. Wei
, F. Boeuf, T. Skotnicki, and H.-S. P. Wong, “CMOS Technology Roadmap
Projection Including Parasitic Effects,”
2009 International Symposium on VLSI Technology, Systems and
Applications (VLSI-TSA2009)
, pp. 78 – 79, Hsinchu, Taiwan, April 27 – 29, 2009.
- H.-S. P. Wong, L. Wei, and J. Deng, “The Future of CMOS
Scaling – Parasitics Engineering and Device Footprint Scaling,” invited
paper,
2008 International Conference on Solid State and Integrated Circuit
Technology (ICSICT2008),
pp. 21 – 24, Beijing, China, October 20 – 23, 2008.
- L. Wei, D. Frank, L. Chang, H.-S. P. Wong, “An Analytical Model
for Intrinsic Carbon Nanotube FETs,”
the 38th European Solid-State Device Research Conference (ESSDERC2008),
pp.222 – 225, Edinburgh, United Kingdom, September 15 – 19, 2008.
- J. Deng, L. Wei, L.-W. Chang, K. Kim, C.-T. Chuang, and H.-S. P.
Wong, "Extending Technology Roadmap by Selective Device Footprint Scaling
and Parasitics Engineering," 2008
International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA2008),
pp. 159 – 160, Hsinchu, Taiwan, April 21 – 23, 2008.
- L. Wei, J. Deng, and H.-S. P. Wong, “1-D and 2-D Devices
Performance Comparison including Parasitic Gate Capacitance and Screening
Effect,”
2007 IEEE International Electron Devices Meeting (IEDM2007)
, pp. 741 – 744, Washington, D. C., USA, December 10 – 12, 2007.
- L. Wei, J. Gao, L. Ji, Z. Chen “A New Structure of Low-Noise CMOS Differential
Amplifier”,
the 6th International Conference on ASIC (ASICON2005),
pp. 360 – 364, vol. 1, Shanghai, October 24 – 27, 2005.
- X. Jiang, J. Wang, X. Wang, R. Wang, B Cheng, A. Asenov, L. Wei,
and R. Huang, “New Assessment Methodology Based on Energy Delay Yield Co
optimization for Nanoscale CMOS Technology,”IEEE Transactions on Electron Devices (TED), vol. 62, no. 6, pp. 1746-1753, June 2015.
- Z. Zhang, A. Lin, N. Patil, H. Wei, L. Wei, H.-S. P. Wong, and
S. Mitra, “Robust Digital VLSI using Carbon Nanotubes”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems
(TCAD), vol. 31, No. 4, pp. 453-471, 2012.
- H. Debéda, I. Rua, E. Fernandes*, S. Zarabi*, D.
Nairn, L. Wei, and A. Salehian, “Printed MEMS-based Self-contained
Piezoelectric-based Monitoring Device for Smart Grids,” the 17th International Conference on Micro and Nanotechnology for Power Generation and Energy Conversion Applications (PowerMEMS2017), Kanasawa, Japan, Nov 2017.
- I. Rua, H. Debéda, E. Fernandes*, S. Zarabi*, D.
Nairn, L. Wei, and A. Salehian, “ Optimization of the fabrication of a low
frequency energy harvester made of printed PZT layers on a meander shape
stainless substrate,”
2017 Conference on Design, Test, Integration and Packaging for
MEMS/MOEMS
(DTIP2017), May 2017.
- L. Yu, O. Mysore, L. Wei, L. Daniel, D. Antoniadis, I. Elfade, D.
Boning, “An Ultra-Compact Virtual Source FET Model for Deeply-Scaled
Devices: Parameter Extraction and Validation for Standard Cell Libraries
and Digital Circuits,” 18th Asia and South Pacific Design Automation
Conference (ASPDAC 2013), pp.521-526, 2013
- L. Yu, L. Wei, D. Antoniadis, I. Elfadel, D. Boning, “Statistical
Modeling with the Virtual Source MOSFET Model,” pp1454-1457, 2013 The
Design, Automation, and Test in Europe Conference (DATE 2013), 2013.
- C. Sun, C.-H. Chen, G. Kurian, L. Wei, J. Miller, A. Agarwal,
L.-S. Peh and V. Stojanovic , “DSENT – A Tool Connecting Emerging Photonics
with Electronics for Opto-Electronic Networks-on-Chip Modeling,”
6th ACM/IEEE International Symposium on Networks-on-Chip (NOCS
2012
),
Lyngby, Denmark, May 9-11, 2012.
- G. Kurian, C. Sun, C.-H. Chen, J. E. Miller, J. Michel, L.Wei,
D. A. Antoniadis, L.-S. Peh, L. Kimerling, Vladimir Stojanovic and Anant
Agarwal, “Cross-layer Energy and Performance Evaluation of a Nanophotonic
Manycore Processor System using Real Application Workloads,”
26th IEEE International Parallel & Distributed Processing Symposium
(IPDPS2012), pp. 1117-1130, 2012.
- H. –S. P. Wong, S. Mitra, D. Akinwande, C. Beasley, Y. Chai, H. –Y.
Chen, X. Chen, G. Close, J. Deng, A. Hazeghi, J. Liang, A. Lin, L. S.
Liyanage, J. Luo, J. Parker, N. Patil, M. Shulaker, H. Wei, L. Wei,
J. Zhang, “Carbon Nanotube Electronics – Materials, Devices, Circuit,
Design, Modeling, and Performance Projection,”
IEEE International Electron Devices Meeting (IEDM 2011
)
.
- H. Wei, J. Zhang, L. Wei, N. Patil, A. Lin, M.
Shulaker, H.-Y. Chen, H. -S. P. Wong and S. Mitra, “Carbon Nanotube
Imperfection-Immune Digital VLSI: Frequently Asked Questions Updated,”2011 International Conference on Computer-Aided Design (ICCAD2011), pp.
227-230, November 7-10, 2011.
- X. Chen, A. Lin, L. Wei, N. Patil, H. Wei, H.-Y. Chen, S. Mitra,
and H.-S. P. Wong, “Carbon-Based Nanomaterial for Nanoelectronics”, the Electrochemical Society Trans. vol. 35, pp. 259-269, 2011.
- H.-Y. Chen, N. Patil, A. Lin, L. Wei, Ca. Beasley, J. Zhang, X. Chen,
H. Wei, L. Liyanage, M. SHulaker, S. Mitra, H.-S. P. Wong, “Carbon
electronics- From material synthesis to circuit demonstration,” “CMOS
Technology Roadmap Projection Including Parasitic Effects,” 2011
International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA2011
)
, pp. 1-2, Hsinchu, Taiwan, April 25 – 27, 2011.
- L. Wei and K. Sheikh*, “Impact of Process Imperfection of CNFET on Circuit-level Performance and Proposal to Improve using Approximate Circuits”, 2018 International Conference on Solid-State and Integrated Circuit Technology (ICSICT2018) (Invited talk)
- L. Wei and K. Sheikh*, “Using Approximate Circuit to Improve Process Induced Failure in CNFET Circuits,” The 6th Carbon Nanotube Thin Film Electronics and Applications Symposium (CNTFA18) (Invited talk)
- A. Tosson*, S. Yu, M. Anis and L. Wei, “1T2R: A Novel
Memory Cell Design to Resolve Single-Event Upset in RRAM Arrays,” paper
918, 2017 IEEE 12th International Conference on ASIC (ASICON2017) (Invited paper)
- L. Wei, “Technology Assessment based on Device and Circuit
Interaction and Optimization,” CMOS Emerging Technologies Research
, Vancouver, Canada, 2015 (Invited talk)
- L. Wei, “Technology Assessment based on Device and Circuit
Interaction and Optimization, ” seminar at IEEE Montreal Circuits and
Systems Chapter, Montreal, Canada, Nov 2014 (Seminar)
- L. Wei, “Nanoelectronics: Technology Assessment and Projection
at the Device, Circuit, and System Level.” (Seminar)
- L. Wei, “Device and Circuit Interactive Design.” (Seminar)
- L. Wei and H.-S. Philip Wong, “Compact Modeling Aided Technology Design
and Projection Considering System-Level Performance,” 2009 MOS Modeling and
Parameter Extraction Working Group (MOS-AK/GSA), Baltimore, USA, Dec, 2009. (Invited talk)
Highly Qualified Personnel (HQP) under my direct supervisions are marked with *
Referred journal publications with major contributions
Referred conference publications with major contributions
Referred journal and conference publications with collaborative contributions
Seminar and invited talks
Stanford University, USA (Jan 2009), Johns Hopkins University, USA (Feb 2009), University of Southern California, USA (Mar 2009), University of California San Diego, USA (Mar 2009), University of California Riverside, USA (Mar 2009), Carnegie Mellon University, USA (Mar 2009), Shanghai Jiaotong University, China (Apr 2009), University of California Berkeley, USA (Apr 2009)
Pennsylvania State University, USA (Nov 2011), Semiconductor Manufacturing International Corporation, China, (Jan 2012), Chinese University of Hong Kong, Hong Kong (Jan 2012), Altera Corporation, USA (Feb 2012), Cornell University, USA (Mar 2012), University of Toronto, Canada (Apr 2012), IBM Semiconductor Research and Development Center, USA (May 2012), Qualcomm Research Center, USA (May 2012), University of Waterloo, Canada (Jul 2012), University of Houston, USA (Aug 2012).