Selected
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2013
- M. Yang, N. P. Papadopoulos, W. Wong, and M. Sachdev, "A Novel Voltage-Programmed Pixel Circuit Utilizing VT-Dependent Charge-Transfer to Improve Stability of AMOLED Display," IEEE/OSA Journal of Display Technology, accepted.
- J.S. Shah, D. Nairn and M. Sachdev, "An Energy-Efficient Offset-Cancelling Sense Amplifier," Circuits and Systems-II: Express Briefs, IEEE Transactions on, accepted.
- A. Neale, and M. Sachdev, "A New SEC-DED Error Correction Code Subclass for Adjacent MBU Tolerance in Embedded Memory," Device and Material Reliability, IEEE Transactions on, vol.13, no. 1, pp.223-230, March 2013.
- P. Chuang, M. Sachdev, V. Gaudet, "A 167-ps 2.34-mW Single-Cycle 64-bit Binary Tree Comparator with Constant-Delay Logic in 65-nm CMOS," Circuits and Systems-I: Regular Papers, IEEE Transactions on, accepted.
2012
- D. Rennie, D. Li, M. Sachdev, B.L. Bhuva, S. Jagannathan, Wen ShiJie, R. Wong, "Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS," Circuits and Systems I: Regular Papers, IEEE Transactions on, vol.59, no.8, pp.1626-1634, Aug. 2012.
- T. Charania, A. Opal, M. Sachdev, "Analysis and Design of On-Chip Decoupling Capacitors," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, accepted.
- P. Chuang, D. Li, M. Sachdev, "A Constant Delay Logic Style," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, accepted.
- P. Chuang, D. Li, M. Sachdev, "A Low-Power, High-Performance, Single-Cycle, Tree Based 64-Bit Binary Comparator," Circuits and Systems II (TCAS-II), IEEE Transaction on, vol. 59, no. 2, pp. 108-112, Feb. 2012
2011
- M. Sharifkhani, E. Rahiminejad,S. Jahinuzzaman, and M. Sachdev, "A compact hybrid current/voltage sense amplifier with offset cancellation for high-speed SRAMs," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, no.5, pp.883-894, May 2011.
- M. Nummer, and M. Sachdev, "Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths," Electronic Testing, Journal of, vol. 27, no.1, pp 9-17, Feb. 2011.
2009
- S. M. Jahinuzzaman, J. S. Shah, D. J. Rennie, and M.
Sachdev, "Design and Analysis of A 5.3-pJ 64-kb Gated
Ground SRAM With Multiword ECC," Solid-State Circuits, IEEE
Journal of , vol.44, no.9, pp.2543-2553, Sept. 2009.
- M. Sharifkhani and M. Sachdev, "An energy efficient 40
Kb
SRAM module with extended read/write noise margin in 0.13 um CMOS,"
IEEE J. Solid-State Circuits, vol. 44., no. 2, pp. 620-630, Feb. 2009.
- M. Sharifkhani and M. Sachdev, "SRAM cell stability: a
dynamic perspective," IEEE J. Solid-State Circuits, vol. 44., no. 2,
pp. 609-619, Feb. 2009.
1999-2008- M.
Maymandi-Nejad, and Manoj Sachdev, "DTMOS Technique for Low-Votlage
Analog Circuits", IEEE Trans. on Very Large Scale Integration (VLSI)
Systems, vol 14, no. 10, Oct. 2006.
- A. Keshavarzi, J. W. Tschanz, S. Narendra, V. De, W. R.
Daasch, K. Roy, M. Sachdev, C. F. Hawkins, "Leakage
and process variation effects in current testing on future CMOS circuits,"
IEEE Design and Test of Computers, vol. 19, no. 5, Sep.-Oct., 2002.