CMOS Design and Reliability Group

Selected Recent Publications

[ Books and Book Chapters | Theses | Journal Papers | Conference Papers ]

Copyright Notice: (c)20xx IEEE. All the papers below have been copyrighted to IEEE or the publishers of the corresponding journals and conference proceedings. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE or the appropriate publisher.

2013

M. Yang, N. P. Papadopoulos, W. Wong, and M. Sachdev, "A Novel Voltage-Programmed Pixel Circuit Utilizing VT-Dependent Charge-Transfer to Improve Stability of AMOLED Display," IEEE/OSA Journal of Display Technology, accepted.

J.S. Shah, D. Nairn and M. Sachdev, "An Energy-Efficient Offset-Cancelling Sense Amplifier," Circuits and Systems-II: Express Briefs, IEEE Transactions on, accepted.

A. Neale, and M. Sachdev, "A New SEC-DED Error Correction Code Subclass for Adjacent MBU Tolerance in Embedded Memory," Device and Material Reliability, IEEE Transactions on, vol.13, no. 1, pp.223-230, March 2013.

P. Chuang, M. Sachdev, V. Gaudet, "A 167-ps 2.34-mW Single-Cycle 64-bit Binary Tree Comparator with Constant-Delay Logic in 65-nm CMOS," Circuits and Systems-I: Regular Papers, IEEE Transactions on, accepted.

2012

D. Rennie, D. Li, M. Sachdev, B.L. Bhuva, S. Jagannathan, Wen ShiJie, R. Wong, "Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS," Circuits and Systems I: Regular Papers, IEEE Transactions on, vol.59, no.8, pp.1626-1634, Aug. 2012.

T. Charania, A. Opal, M. Sachdev, "Analysis and Design of On-Chip Decoupling Capacitors," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, accepted.

P. Chuang, D. Li, M. Sachdev, "A Constant Delay Logic Style," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, accepted.

P. Chuang, D. Li, M. Sachdev, "A Low-Power, High-Performance, Single-Cycle, Tree Based 64-Bit Binary Comparator," Circuits and Systems II (TCAS-II), IEEE Transaction on, vol. 59, no. 2, pp. 108-112, Feb. 2012

2011

M. Sharifkhani, E. Rahiminejad,S. Jahinuzzaman, and M. Sachdev, "A compact hybrid current/voltage sense amplifier with offset cancellation for high-speed SRAMs," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, no.5, pp.883-894, May 2011.

M. Nummer, and M. Sachdev, "Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths," Electronic Testing, Journal of, vol. 27, no.1, pp 9-17, Feb. 2011.

2009

S. M. Jahinuzzaman, D. J. Rennie, and M. Sachdev, "A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability," Nuclear Science, IEEE Transaction on , vol.56, no.6, pp.3768-3773, Dec. 2009.

S. M. Jahinuzzaman, J. S. Shah, D. J. Rennie, and M. Sachdev, "Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC," Solid-State Circuits, IEEE Journal of , vol.44, no.9, pp.2543-2553, Sept. 2009.

S. M. Jahinuzzaman, M. Sharifkhani, and M. Sachdev, "An analytical model for soft error critical charge of nanometric SRAMs ," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.17, no.9, pp.1187-1195, Sept. 2009.

N. Mohan, M. Sachdev, "Low-Leakage Storage Cells for Ternary Content Addressable Memories," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 5, pp. 604-612, May 2009.

N. Mohan, W. Fung, D. Wright, M. Sachdev, "A Low-Power Ternary CAM with Positive-Feedback Match Line Sense Amplifiers," IEEE Transactions on Circuits and Systems I (TCAS-I): Regular Papers, vol. 56, no. 3, pp. 566-573, Mar. 2009.

M. Sharifkhani and M. Sachdev, "An energy efficient 40 Kb SRAM module with extended read/write noise margin in 0.13 um CMOS," IEEE J. Solid-State Circuits, vol. 44., no. 2, pp. 620-630, Feb. 2009.

M. Sharifkhani and M. Sachdev, "SRAM cell stability: a dynamic perspective," IEEE J. Solid-State Circuits, vol. 44., no. 2, pp. 609-619, Feb. 2009.

1999-2008

H. Sarbishaei, O. Semenov, M. Sachdev, "A New Flip-Flop Based Transient Power Supply Clamp for ESD Protection," IEEE Tran Dev Mat Rel, pp. 358-367, June, 2008.

D. J. Rennie, M. Sachdev, "A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector," Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.55, no.3, pp.796-803, April 2008.

N. Mohan, M. Sachdev, "Low-capacitance and charge-shared match lines for low-energy high-performance TCAMs," IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 2054-2060, Sep. 2007.

M. Elgebaly and M. Sachdev, "Variation-aware adaptive voltage scaling system," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 5, pp. 560-571, May 2007.

M. Sharifkhani and M. Sachdev, "Segmented virtual ground architecture for low-power embedded SRAM," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 2, pp. 196-205, Feb. 2007.

M. Maymandi-Nejad, and Manoj Sachdev, "DTMOS Technique for Low-Votlage Analog Circuits", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol 14, no. 10, Oct. 2006.

A. Pavlov, M. Sachdev and J. Pineda de Gyvez, "Weak cell detection in deep-submicron SRAMs: a programmable detection technique," IEEE J. Solid-State Circuits, vol. 41, no. 10, pp. 2334-2343, Oct. 2006.

N. Mohan, W. Fung, D. Wright, and M. Sachdev, "Design techniques and test methodology for low-power TCAMs," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 6, Jun. 2006.

O. Semenov, A. Vassighi, M. Sachdev, "Impact of self-heating effect on long-term reliability and performance degradation in CMOS circuits," IEEE Trans. on Device and Materials Reliability, vol. 6, No. 1, pp. 17-27, Mar. 2006.

O. Semenov, H. Sarbishaei, V. Axelrad and M. Sachdev, "Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices," Microelectronics Journal, vol. 37, no. 6, pp. 526-533, 2006.

O. Semenov, H. Sarbishaei, V. Axelrad and M. Sachdev, "The impact of CMOS technology scaling on MOSFETs second breakdown: Evaluation of ESD robustness," Microelectronics Reliability Journal, vol. 44, no. 9-11, pp. 1817-1822, 2004.

O. Semenov, M. Obrecht, M. Sachdev, "Evaluation of STI degradation using temperature dependence of leakage current in parasitic SIT MOSFET," Microelectronics Reliability Journal, vol. 44, no. 9-11, pp. 1751-1755, 2004.

A. Vassighi, O. Semenov, M. Sachdev, A. Keshavarzi, C. Hawkins, "CMOS IC Technology Scaling and Its Impact on Burn-in," IEEE Trans. on Device and Materials Reliability, Vol. 4, No. 2, Jun. 2004. Invited paper.

B. Chatterjee, M. Sachdev, A. Keshavarzi, "DFT for Delay Fault Testing of High Performance Digital Circuits," IEEE Design and Test of Computers (Special issue on Design for Yield and Reliability"), pp. 248-258, vol. 21, no. 3, May 2004.

F. H. A. Asgari, M. Sachdev, A low-power reduced swing global clocking methodology," IEEE Trans. on Very Large Scale Integration Systems, Vol. 12, No. 5, pp. 538-545, May 2004.

S. Docking, M. Sachdev, "An analytical equation for the oscillation frequency of high-frequency ring oscillators," IEEE J. Solid-State Circuits, pp. 533-537, vol. 39, no. 3, March 2004.

O. Semenov, A. Vassighi, M. Sachdev, A. Keshavarzi and C.F. Hawkins, "Effect of CMOS technology scaling on thermal management during burn-in," IEEE Transactions on Semiconductor Manufacturing, vol. 16, No. 4, pp. 686-695, Nov. 2003.

M. Nummer, M. Sachdev, "Testing high-performance pipelined circuits with slow-speed testers," ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 8, no. 4, pp. 506-521, October 2003.

M. Maymandi-Nejad, M. Sachdev, “A digitally programmable delay element: Design and analysis,” IEEE Trans. on Very Large Scale Integration Systems, Vol. 11, No. 5, pp. 871-878, October 2003.

M. Maymandi-Nejad, M. Sachdev, “1-bit quantizer with rail to rail input range for sub 1-V delta sigma modulators,” IEE Electronics Letter, Vol. 39, No. 12, pp. 894-895, June 2003.

M. Nummer, M. Sachdev, "A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers," Journal of Electronic Testing: Theory and Applications, pp. 299-314, vol. 19. no. 3, June 2003.

A. Keshavarzi, J. W. Tschanz, S. Narendra, V. De, W. R. Daasch, K. Roy, M. Sachdev, C. F. Hawkins, "Leakage and process variation effects in current testing on future CMOS circuits," IEEE Design and Test of Computers, vol. 19, no. 5, Sep.-Oct., 2002.

O. Semenov, A. Vassighi and M. Sachdev, "Leakage current in sub-quarter micron MOSFET: A perspective on stressed delta IDDQ testing," Journal of Electronic Testing (JETTA), vol. 19, No.3, pp. 341-352, 2003.

S. Docking, M. Sachdev, "A Method to derive an equation for the oscilation frequency of a ring oscillator," IEEE Transactions on Circuits and Systems - I, pp. 259-264, vol. 50, no. 2, February 2003.

W. Chung, T. Lo, M. Sachdev, "A comparative analysis of low-power low-voltage dual edge-triggered flip-flops," IEEE Transactions on VLSI Systems, pp. 913-918, vol. 10, no. 6, December 2002.

M. Maymandi-Nejad, M. Sachdev, “Continuous time common mode feedback technique for sub 1-V analog circuits,” IEE Electronics Letter, Vol. 38, No. 23, pp. 1408-1409, November 2002.

O. Semenov, A. Vassighi and M. Sachdev, "Impact of technology scaling on thermal behavior of leakage current in sub-quarter micron MOSFETs: Perspective of low temperature current testing," Microelectronics Journal, vol. 33, No. 11, pp. 985-994, 2002.

O. Semenov, A. Pradzinski and M. Sachdev, "Impact of Gate Induced Drain Leakage on overall leakage of submicron CMOS VLSI Circuits," IEEE Transactions on Semiconductor Manufacturing, vol.15, No. 1, pp. 9-18, Feb. 2002.

M. Sachdev, "Current-based testing for deep-submicron VLSIs," IEEE Design and Test of Computers, vol. 18, no. 2, Mar.-Apr., 2001.

M. Sachdev, H. Kerkhoff, "Configurations for IDDQ-testable PLAs," IEEE Design and Test of Computers, vol. 16, no. 2, Apr.-Jun., 1999.

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