Selected
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(c)20xx IEEE. All the papers below have been copyrighted to IEEE or the
publishers of the corresponding journals and conference proceedings.
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2013
- M. Yang, N. P. Papadopoulos, C. Lee, W. Wong, and M. Sachdev, "A Novel Voltage-Programmed Pixel Circuit with VT-Shift Compensation for AMOLED Displays," IEEE Custom Integrated Circuits Conference (CICC), 2013, accepted
2012
- N. Papadopoulos, M. Yang, M. Esmaeili-Rad, M. Sachdev, W. Wong, "Discussing Pixel Circuits for Hybrid Sensor and Display Pixel Arrays," The 19th International Display Workshops in conjunction with Asia Display, 2012, accepted
- J.S. Shah, D. Nairn, M. Sachdev, "A Soft Error Robust 32kb SRAM Macro Featuring Access Transistor-Less 8T Cell in 65-nm," IEEE/IFIP Int. Conf. on VLSI and System-on-Chip (VLSI-SoC), pp.275-278, 7-10 Oct. 2012
- T. Charania, P. Chuang, A. Opal, M. Sachdev, "Suppression of on-chip power supply noise generated by a 64-bit static logic ALU block," IEEE/IFIP Int. Conf. on VLSI and System-on-Chip (VLSI-SoC), pp.201-206, 7-10 Oct. 2012
- M. Yang, N. Papadopoulos, W. Wong, M. Sachdev, "A Novel 4-TFT Pixel Circuit with Threshold Voltage Compensation for AMOLED Displays," IEEE Photonics Conference, pp. 516-517, 23-27 Sept. 2012
- P. Chuang, D. Li, M. Sachdev, V. Gaudet, "A 148ps 135mW 64b Adder with Constant-Delay Logic in 65nm CMOS," IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, 9-12 Sept. 2012
2011
- D. Rennie, D. Li, M. Sachdev, B. Bhuva, S. Jagannathan, W. ShiJie, R. Wong, "Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS," Custom Integrated Circuits Conference (CICC), 2011, pp.1-4, 19-21 Sept. 2011
- D. Li, P. Chuang, D. Nairn, M. Sachdev, "Design and Analysis of Metastable-Hardened Flip-Flops in Sub-Threshold Region", International Symposium on Low Power Electronics and Design (ISLPED) 2011, pp. 157- 162, 1-3 Aug. 2011
- T. Charania, P. Chuang, A. Opal, and M. Sachdev, "Analysis of Power Supply Noise Mitigation Circuits," CCECE 2011, 8-11 May 2011
-
D. Li, D. Rennie, P. Chuang, D. Nairn and M. Sachdev, "Design and Analysis of Metastable-Hardened and Soft-Error Tolerant High-Performance, Low-Power Flip-Flops,"
International Symposium on Quality Electronic Design (ISQED), pp. 583-590, 14-16 March 2011 (Best Paper Award)
- A. Neale and M. Sachdev, "Digitally Programmable SRAM Timing for Nano-Scale Technologies,"
International Symposium on Quality Electronic Design (ISQED), pp. 518-524, 14-16 March 2011
2010
- T.
Shakir, D.Rennie, and M. Sachdev, "Integrated Read Assist-Sense Amplifier Scheme for High Performance Embedded SRAMs,"
International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 137-140, 1-4 August 2010
- D.
Li, P.Chuang, and M. Sachdev, "Design of a Novel High-Performance Pre-Discharge Flip-Flop,"
NorthEast Workshop on Circuits and Systems
(NEWCAS), pp. 233-236, 21-23 June 2010
- D.
Li, P.Chuang, and M. Sachdev, "Comparative
Analysis and Study of Metastability on High-Performane Flip-Flops,"
International Symposium on
Quality Electronic Design (ISQED), pp. 853-860, 22-24 March 2010
2009
- S. M. Jahinuzzman, D. J. Rennie, and M. Sachdev,
"Soft error robust impulse and TSPC flip-flops in 90nm CMOS,"
Microsystems and Nanoelectronics Research Conference, 2009. MNRC 2009.
2nd , pp.45-48, 13-14 Oct. 2009 (Best Paper Award)
- J.
S. Shah, S. M. Jahinuzzman, D. Li, P.
Chuang, and M. Sachdev,
"A 64-bit, 2GHz SE Robust Adder Employing
Pseudo-static Logic and Time Redundancy,"
Microsystems and Nanoelectronics Research Conference, 2009. MNRC 2009.
2nd , pp.37-40, 13-14 Oct. 2009
- D. Li, P.Chuang, J. S. Shah, and M.
Sachdev, "Design
of a Novel High-Performance Reduced Clock-Swing Pre-Discharge Flip Flop,"
Microsystems and Nanoelectronics Research Conference, 2009. MNRC 2009.
2nd , pp.41-44, 13-14 Oct. 2009
- H. Sarbishaei, M. Sachdev, "ESD
Protection Circuit for 8.5Gbps I/Os in 90nm CMOS Technology,"
IEEE Custom Interational Circuit Conference (CICC), pp. 697-700, 2009
- P. Chuang, D. Li and M. Sachdev, "Design of a 64-Bit low-energy
high-performance adder using dynamic feedthrough logic," in
Proc. IEEE 2009 International Symposium on Circuits and System.
(ISCAS), Taipei, TW, May 24-27 2009, pp. 3038-3041.
1999-2008
- H. Sarbishaei, S. S. Lubana, O. Semenov, and M. Sachdev,
“A darlington-based SCR ESD protection device for high speed
applications,” in Proc. IEEE Int. Rel. Phys. Symp. 2008, Phoenix, AZ,
pp. 633-634.
- S. M. Jahinuzzaman, M. Sharifkhani, and M. Sachdev,
"Investigation of process impact on soft error susceptibility of
nanometric SRAMs using a compact critical charge model", in Proc. Int.
Symp. on Quality Electronic Design (ISQED) 2008, San Jose, CA, pp.
207-212.
- H. Sarbishaei, O. Semenov and M. Sachdev, “A transient
power supply ESD clamp with CMOS thyristor delay element,” in Proc.
EOS/ESD Symp., Anaheim, CA, 2007, pp. 395-402.
- H. Sarbishaei, O. Semenov and M. Sachdev, “Optimizing
circuit performance and ESD protection for high-speed differential
I/Os,” in Proc. IEEE 2007 Custom Integrated Circuits Conf. (CICC), San
Jose, CA, pp. 149-152.
- M. Sharifkhani, S. M. Jahinuzzaman, and M. Sachdev,
“Dynamic data stability in low-power SRAM design,” in Proc. IEEE 2007
Custom Integrated Circuits Conf. (CICC), San Jose, CA, pp. 237-240. (Won
an AMD/CICC Student Scholarship)
- M. Sharifkhani, and M. Sachdev, "A low power SRAM
architecture based on segmented virtual grounding," in Proc. Int. Symp.
on Low Power Electronics and Design (ISLPED), Tegernsee, Germany, 2006,
pp. 256-261.
- N. Mohan, and M. Sachdev, "Novel ternary storage cells and techniques
for leakage reduction in ternary CAM," in Proc. IEEE Int. SOC
Conference (SOCC), Austin, Texas, Sept. 24-27, 2006, pp. 311-314.
- N. Mohan, W. Fung, and M. Sachdev, "Low-power
priority encoder and multiple match detection circuit for ternary
content addressable memory," in Proc. IEEE Int. SOC
Conference (SOCC), Austin, Texas,Sep. 24-27, 2006, pp. 353-356.
- N. Mohan, W. Fung, D. Wright, and M. Sachdev, "Match
line sense amplifiers with positive feedback for low-power content
addressable memories," in Proc. IEEE Custom Integrated
Circuits Conference (CICC),San Jose, CA, Sep. 10-13, 2006, pp. 297-300.
- M. Sharifkhani, and M. Sachdev, "A phase-domain
continuous-time 2nd-order delta-sigma frequency digitizer," in Proc.
IEEE Custom Integrated Circuits Conference (CICC),San Jose, CA, Sept.
11-13, 2006, pp. 205-208.
- M. Sharifkhani, S. M. Jahinuzzaman, and M. Sachdev,
“Dynamic data stability in SRAM cells and its implications on data
stability tests,” in Proc. IEEE Int. Workshop on Memory Technology,
Design and Testing 2006 (MTDT’06), Taipei, Taiwan, August 2-4, 2006,
pp. 55-61. (Invited)
- N. Mohan, and M. Sachdev, "A
comparative study of low-power techniques for ternary CAMs,"
Proceedings of the IEEE Int. Conference for Upcoming Engineers (ICUE),
Waterloo, ON, Canada, May 13-14, 2006.
- A. Pavlov, M. Azimane, J. Pineda de Gyvez and M. Sachdev, "Word
Line Pulsing Technique for Stability Fault Detection in SRAM cells,"
in Proc. IEEE Int. Test Conference (ITC-2005), Austin, TX, Nov. 2005,
pp. 1-10 .
- A. Pavlov, M. Azimane, J. Pineda de Gyvez and M. Sachdev, "Programmable
Techniques for Cell Stability Test and Debug in Embedded SRAMs,"
in Proc. IEEE Custom Integrated Circuits Conference (CICC), San Jose,
CA, Sept. 2005, pp. 443-446.
- O. Semenov, H. Sarbishaei, M. Sachdev, "Analysis
and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in
Environment," IEEE ISQED, San Jose, CA, pp. 427-432, 2005.
- A. Pavlov, M. Sachdev, J. Pineda, "An
SRAM weak cell fault model and a DFT technique with a programmable
detection threshold," IEEE ITC 2004, Charlotte, NC, pp.
1106-1115, 2004.
- B. Chatterjee, M Sachdev, A. Keshavarzi, "A
DFT Technique for Delay Fault Testability and Diagnostics for 32-bit
High Performance CMOS ALUs," IEEE ITC 2004, Charlotte, NC,
2004.
- M. Elgebaly, M Sachdev, "Efficient
Adaptive Voltage Scaling System Through On-Chip Critical Path Emulation,"
Proc. IEEE ISLPED 2004, pp. 375-380, Newport Beach, Aug. 9-11, 2004.
- B. Chatterjee, M Sachdev, R. Krishnamurthy, "A CPL
Based Dual Supply 32-bit ALU Design for Sub-180nm CMOS Technologies,"
Proc. IEEE ISLPED 2004, pp. 248-251, Newport Beach, Aug. 9-11, 2004.
- A. Vassighi, A. Keshavarzi, S. Narendra, G. Schrom, Y. Ye,
S. Lee, G. Chrysler, M. Sachdev, V. De, "Design
optimizations for microprocessors at low temperature," Invited
Paper, Proc. Design Automation Conference (DAC), pp. 2-5,
June, 2004.
- C. Kwong, B. Chatterjee, M. Sachdev, "Modeling
and Designing Energy-Delay Optimized Wide Domino Circuits,"
Proc. IEEE ISCAS 2004, Vancouver, pp. 921-924, May 23-26, 2004.
- N. Mohan, M. Sachdev, "Low
Power Dual Matchline Ternary Content Addressable Memory,"
Proc. IEEE ISCAS 2004, Vancouver, pp. 633-636, May 23-26, 2004.
- N. Mohan, M. Sachdev, "A
Static Power Reduction Technique for Ternary Content Addressable
Memories," Proc. IEEE CCECE 2004, Niagara Falls, pp. 711-714,
May 2-5, 2004.
- A. Vassighi, O. Semenov and M. Sachdev, "Thermal
runaway avoidance during burn-in," IEEE IRPS 2004, Phoenix,
pp. 655-656, April 25 - 29, 2004.
- B. Chatterjee, M. Sachdev, R. Krishnamurthy, "Leakage
control Techniques for Designing Robust Low-Power Wide-OR Domino Logic
for sub-130nm CMOS Technologies," Proc. IEEE ISQED 2004, San
Jose, pp. 415-420, March 22-24, 2004.
- S. Ardalan, M. Sachdev, "An
overview of substrate noise reduction techniques," Proc. IEEE
ISQED 2004, San Jose, pp. 291-296, March 22-24, 2004.
- W. Fung and M. Sachdev, "High Performance Priority Encoder for
Content Addressable Memories," Proceedings of Micronet
R&D Annual Workshop 2004, pp. 49-50, 2004.
- A. Vassighi, O. Semenov, M. Sachdev and A. Keshavarzi, "Thermal
management of high performance microprocessors in burn-in environment,"
IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems
(DFT'03), Cambridge, MA, USA, pp. 313-319, Nov. 2003.
- O. Semenov, A. Vassighi, M. Sachdev, A. Keshavarzi and
C.F. Hawkins, "Burn-in
temperature projections for deep sub-micron technologies,"
IEEE Int. Test Conference, pp. 95-104, Oct. 2003.
- D. Wright, and M. Sachdev "Transistor-Level
Fault Analysis and Test Algorithm Development for Ternary Dynamic
Content Addressable Memories", Proc. IEEE ITC 2003, Charlotte
N.C., pp. 39-47, 2003.
- M. Elgebaly, A. Fahim, I. Kang, and M. Sachdev "Robust
and efficient dynamic voltage scaling architecture," Proc.
IEEE International SOC Conference, pp. 155-158, 17-20 Sep. 2003.
- M. Nummer, and M. Sachdev "DFT
for testing high-performance pipelined circuits with slow-speed testers,"
Proc. Design, Automation and Test in Europe Conference, pp. 212-217,
2003.
- B. Chatterjee, M. Sachdev, S. Hsu, R. Krishnamurthy, S.
Borkar, "Effectiveness
and scaling trends of leakage control techniques for sub-130nm CMOS
technologies," Proc. IEEE ISLPED 2003, Seoul, pp. 122-127,
August 25-27, 2003.
- S. Hsu, B. Chatterjee, M. Sachdev, A. Alvandpour, R.
Krishnamurthy, S. Borkar,"A 90nm 6.5GHz 256x64b dual supply register
file with split decoder scheme," Proc. IEEE VLSI Circuits
Symposium 2003, Hawaii, pp. 237-238, June 12-14, 2003.
- A. Pavlov, M. Sachdev and J.
Pineda, "A
parametric-stability fault model for embedded SRAMs," Poster
Presentation, 8th IEEE European Test Workshop 2003, Maastricht, The
Netherlands, 2003.
- A. Vassighi, O. Semenov, M. Sachdev and A. Keshavarzi, "Effect of
static power dissipation in burn-in environment on yield of VLSI,"
IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems
(DFT'02), Vancouver, Canada, pp. 12-19, Nov. 2002.
- O. Semenov, A. Pavlov, and M. Sachdev, "Sub-quarter
micron SRAM cells stability in low-voltage operation: A comparative
analysis," IEEE Int. Integrated Reliability Workshop (IRW),
pp. 168-171, Oct. 2002.
- B. Chatterjee, M. Sachdev, A. Keshavarzi, "A DFT
technique for low frequency delay fault testing in high performance
digital circuits," Proc. IEEE ITC 2002, Baltimore, pp.
1130-1139, October 7-10, 2002.
- M. Sachdev "Multi Gigahertz digital test challenges and
techniques," Proc. International Test Conference, pp. 1231,
7-8 Oct. 2002.
- M. Elgebaly, and M. Sachdev "A
leakage tolerant energy efficient wide domino circuit technique,"
Proc. Midwest Symposium on Circuits and Systems, pp. 487-490, 4-7 Aug.
2002.
- R. Krishnamurthy, S. Hsu, M. Anders, B. Bloechel, B.
Chatterjee, M. Sachdev, S. Borkar, "Dual supply voltage clocking for 5 GHz 130
nm integer execution core," Proc. IEEE VLSI Circuits
Symposium 2002, Kyoto, pp. 128-129, June 13-15, 2002.
- S. Rusu, M. Sachdev, C. Svensson, B. Nauta, "Trends
and challenges in VLSI technology scaling towards 100 nm," Tutorial,
Proc. DAC 2002, pp. 16-17, 7-11 Jan. 2002.
- M. Elgebaly, M. Sachdev, "A
sub-0.5 V dynamic threshold PMOS (DTPMOS) scheme for bulk CMOS
technologies," Proc. International Conference on
Microelectronics, pp. 75-78, 29-31 Oct. 2001.
- A. Vassighi, O. Semenov, M. Sachdev and A. Keshavarzi, "Impact of
power dissipation on burn-in test environment for sub-micron
technologies," IEEE Int. Workshop on Yield Optimization and
Test (YOT), pp. 1-5, Oct. 2001.
- J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev,
V. De, "Comparative
delay and energy of single edge-triggered & dual edge-triggered
pulsed flip-flops for high-performance microprocessors,"
Proc. ISLPED 2001, pp. 147-152, August, 2001.
- O. Semenov, B. Chatterjee and M. Sachdev, "Impact of
technology scaling on bridging fault modeling in CMOS circuits,"
IEEE Int. Workshop on Defect Based Testing (DBT), pp. 45-50, April 2001.
- M. Nummer, M. Sachdev, "A
methodology for testing high-performance circuits at arbitrarily low
test frequency," Proc. IEEE VLSI Test Symposium, pp. 68-74,
23 Apr.-3 May, 2001.
- O. Semenov, A. Pradzinski and M. Sachdev, "Contribution
of Gate Induced Drain Leakage to overall leakage and yield loss in
digital submicron VLSI Circuits," IEEE Int. Integrated
Reliability Workshop (IRW), pp. 49-53, Oct. 2001.
- A. Keshavarzi, K. Roy, M. Sachdev, C. F. Hawkins, K.
Soumyanath, V. De, "Multiple-parameter CMOS IC testing with
increased sensitivity for IDDQ," Proc. International Test
Conference, pp. 1051-1059, 3-5 Oct. 2000.
- H. Speek, H. G. Kerkhoff, M. Sachdev, M. Shashaani, "Bridging
the testing speed gap: design for delay testability," Proc.
European Test Workshop, pp. 3-8, 23-24 May, 2000.
- W. Chung, M. Sachdev, "A comparitive analysis of dual edge
triggered flip-flops," Proc. IEEE CCECE 2000, Halifax, pp.
564-568, May 7-10, 2000.
- O. Semenov and M. Sachdev, "Impact of
technology scaling on bridging fault detections in sequential and
combinational CMOS circuits," IEEE Int. Workshop on Defect
Based Testing (DBT), pp. 36-42, April 2000.
- O. Semenov and M. Sachdev, "Impact of
technology scaling on bridging fault detections," IEEE
Canadian Conference on Electrical and Computer Engineering, pp.
199-203, March 2000.
- M. Shashaani, M. Sachdev, "A DFT
technique for high performance circuit testing," Proc. ITC
1999, Atlantic City, NJ, pp. 276-285, September 28-30, 1999.
- M. Sachdev, M. Shashaani, "A
comparitive analysis of high-speed digital test techniques,"
Proc. IEEE CCECE 1999, Edmonton, pp. 379-384, May 9-12, 1999.
- R. J. W. T. Tangelder, H. de Vries, R. Rosing, H. G.
Kerkhoff, M. Sachdev, "Jitter and decision-level noise separation
in A/D converters," Proc. IEEE Instrumentation and
Measurement Technology Conference, vol. 3, pp. 1558-1562, 24-26 May
1999.
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