A. Barsoum and M. A. Hasan, “Enabling Data Dynamic and Indirect Mutual Trust for Cloud Computing Storage Systems,” IEEE Trans. on Parallel and Distributed Systems, to appear.

M. A. Hasan and C. Negre, “Multi-way Splitting Method for Toeplitz Matrix Vector Product,” IEEE Trans. Computers, to appear.

M. Cenk, M. A. Hasan, and C. Negre, “Improved Three-Way Split Formulas for Binary Polynomial and Toeplitz Matrix Vector Products", IEEE Trans. Computers, to appear.

J. Adikari, A. Barsoum, M. A. Hasan, A. H. Namin, C. Negre, "Improved Area-Time Trade-offs for Field Multiplication using Optimal Normal Bases," IEEE Trans. Computers, to appear.

M. A. Hasan and C. Negre, “Sequential Multiplier with Sub-linear Complexity,” J. Cryptogr. Eng., vol. 2, pp. 91-97, Sept. 2012.

M. A. Hasan, A. Namin and C. Negre, “Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials,” IEEE Trans. VLSI Systems, vol. 30, no. 3, pp. 449-458, Mar. 2012.

M. A. Hasan, N. Meloni, A. Namin, and C. Negre, “Block Recombination Approach for Subquadratic Space Complexity Binary Field Multiplication Based on Toeplitz Matrix-Vector Product,” IEEE Trans. Computers, vol. 61, no. 2, pp. 151-163, Feb. 2012.

N. Meloni, C. Negre and M. A. Hasan, "High performance GHASH and impacts of a class of unconventional bases," pp. 201-218, vol. 1, J. Cryptogr. Eng., Nov. 2011.

C. Moreno and M. A. Hasan, "SPA-resistant binary exponentiation with optimal execution time," pp. 87-99, vol. 1, J. Cryptogr. Eng., Aug. 2011.

M. A. Hasan and C. Negre, “Low Space Complexity Multiplication over Binary Fields with Dickson Polynomial Representation,” IEEE Trans. Computers, vol. 60, no. 4, April 2011.

A. Dominguez-Oviedo, M. A. Hasan and B. Ansari, “Fault-Based Attack on Montgomery’s Ladder Algorithm,” J. of Cryptology, vol. 24, no. 2, pp. 346-374, April 2011.

A. Dominguez-Oviedo and M. A. Hasan, “Algorithm-level Error Detection for ECSM,” J. of Cryptographic Eng., vol. 1, no. 1, pp. 57-69, April 2011.

S. Bayat-Sarmadi and M. A. Hasan, “Concurrent Error Detection in Finite Field Arithmetic Operations using Pipelined and Systolic Architectures,” IEEE Transactions on Computers, vol. 58, no. 11, pp. 1553-1567, November 2009.

A. Dominguez-Oviedo and M. A. Hasan, “Error-detection and Fault-tolerance in ECSM Using Input Randomization,” IEEE Trans. Dependable and Secure Computing, vol. 6, no. 3, pp. 175-187, July-September, 2009.

H. Fan and M. A. Hasan, “Alternative to the Karatsuba Algorithm for Software Implementation of GF(2n) Multiplication,” IET Information Security, vol. 3, no. 2, pp. 60-65,  June 2009.

B. Ansari and M. A. Hasan, "High-Performance Architecture of Elliptic Curve Scalar Multiplication," IEEE Transactions on Computers, vol. 57, no. 11, pp. 1443-1453, Nov, 2008.

N. Ebeid and M. A. Hasan, "On t-adic Representations of Integers," Designs, Codes and Cryptography, pp. 271-296, Dec. 2007.

H. Fan and M. A. Hasan, "Subquadratic Computational Complexity Schemes for Extended Binary Field Multiplication Using Optimal Normal Bases," IEEE Trans. Computers, vol. 56, no. 10, pp. 1435-1437, Oct. 2007. 

H. Fan and M. A. Hasan, "Comments on 'Five, Six, and Seven-Term Karatsuba-Like Formulae'," IEEE Trans. Computers, vol. 56, no. 5, pp. 716-717, May 2007.

S. Bayat-Sarmadi and M. A. Hasan, "On Concurrent Detection of Errors in Polynomial Basis Multiplication," IEEE Trans. VLSI, vol. 15, no. 4, pp. 413-426, Apr. 2007. 

H. Fan and M. A. Hasan, "A New Approach to Sub-quadratic Space Complexity Parallel Multipliers for Extended Binary Fields," IEEE Trans. Computers, vol. 56, no. 2, pp. 224-233, Feb. 2007.

N. Ebeid and M. A. Hasan, "On Binary Signed Digit Representations of Integers," Designs, Codes and Cryptography, pp. 43-65, Jan. 2007.

J. Chung and M. A. Hasan, "Low-Weight Polynomial Form Integers for Efficient Modular Multiplication," IEEE Trans. Computers, vol. 56, no. 1, pp. 44-57, Jan. 2007.

H. Fan and M. A. Hasan, "Fast Bit Parallel Shifted Polynomial Basis Multipliers in GF(2ⁿ)," IEEE Trans. Circuits & Systems--I, vol. 53, no. 12, pp. 2606-2615, Dec. 2006.

H. Fan and M. A. Hasan, "Relationship Between GF(2^m) Montgomery and Shifted Polynomial Basis Multiplication Algorithms," IEEE Trans. Computers, vol. 55, no. 9, pp. 1202-1206, Sept. 2006.

A. Reyhani-Masoleh and M. A. Hasan, "Fault Detection Architectures for Field Multiplication Using Polynomial Bases," IEEE Trans. Computers,  vol. 55, no. 9, pp. 1089-1103, Sept. 2006.

A. Daneshbeh and M. A. Hasan, "A class of scalable unidirectional bit serial systolic architectures for multiplicative inversion and division over GF(2^m)," IEEE Trans. Computers, Vol. 54, No. 3, pp. 370-380, March 2005.

A. Reyhani-Masoleh and M. A. Hasan, "Low Complexity Word-Level Sequential Normal Basis Multipliers,'' IEEE Trans. Computers,  Vol. 54, No. 2, pp. 98-110, February 2005.

A. Reyhani-Masoleh and M. A. Hasan, "Low Complexity Bit Parallel Polynomial Basis Multiplication over GF(2^m),'' IEEE Trans. Computers, Vol. 53, No. 8, pp. 945-959,  August 2004.

A. Reyhani-Masoleh and M. A. Hasan, "Towards Fault Tolerant Cryptographic Computations over Finite Fields", ACM Trans. Embedded Computing Systems, Special Issue on Embedded Systems and Security, Volume 3, Issue 3, pp. 593 - 613, August 2004.

A. Reyhani-Masoleh and M. A. Hasan, "Efficient Digit Serial Normal Basis Multipliers over Binary Extension Fields", ACM Trans. Embedded Computing Systems,   Special Issue on Embedded Systems and Security, Volume 3, Issue 3,  pp. 575-592, August 2004.

A. Reyhani-Masoleh and M. A. Hasan, "Fast Normal Basis Multiplication Using General Purpose Processors", IEEE Trans. Computers, pp. 1379-1390, November 2003.

A. Reyhani-Masoleh and M. A. Hasan, "Efficient Multiplication Beyond Optimal Normal Bases," IEEE Trans. Computers, Special Issue on Cryptographic Hardware and Embedded Systems, pp. 428-439, April 2003.

H. Wu, M. A. Hasan, I. F. Blake, S. Gao, "Finite Field Multiplier Using Redundant Representation," IEEE Trans. Computers, pp. 1306-1316, vol. 51, No. 11, November 2002.

H. Wu, M. A. Hasan and I. F. Blake, "Low Complexity Parallel Multipliers in F_qn over F_q," IEEE Trans. Circuits & Systems-Part I, Fundamental Theory & Applications, pp. 1009-1013, July 2002.

A. Reyhani-Masoleh and M. A. Hasan, "A New Construction of Massey-Omura Parallel Multiplier over GF(2^m)," IEEE Transactions on Computers, pp. 511-520, May 2002.

H. Wu and M. A. Hasan, "Efficient Exponentiation Using Dual Basis," IEEE Trans. VLSI Systems, pp. 874-879, December 2001.

M. A. Hasan, "Power Analysis Attacks and Algorithmic Approaches to Their Countermeasures for Koblitz Curve Crypto-systems," IEEE Trans. Computers, pp. 1071-1083, October 2001.

A. G. Wassal and M. A. Hasan, "Low-Power System-Level Design of VLSI Packet Switching Fabrics", IEEE Trans. Computer Aided Design, pp. 723-738, June 2001.

A. G. Wassal and M. A. Hasan, "Prioritized ATM Switches On-board Satellites: Architectural Analysis and Design," IEE Proceedings- Communications, pp. 277-284, October 2000.

M. A. Hasan and A. G. Wassal, "VLSI Algorithms, Architectures and Implementation of a Versatile GF(2^m) Processor," IEEE Trans. Computers, pp. 1064-1073, October 2000.

M. A. Hasan, "Look-up Table-Based Large Finite Field Multiplication in Memory Constrained Cryptosystems," IEEE Trans. Computers, pp.749-758, July 2000.

H. Wu and M. A. Hasan, "Closed-Form Expression for the Average Weight Signed-Digit Representation," IEEE Trans. Computers, vol. 48, pp. 848-851, August 1999.

H. Wu, M. A. Hasan and I. F. Blake, "Low Complexity Bit-Parallel Finite Field Multipliers," IEEE Trans. Computers, pp. 1223-1234, November 1998.

M. A. Hasan and M. Ebtedaei, "Efficient Architectures for Computations over Variable Dimensional Galois Fields," IEEE Trans. Circuits and Systems-Part I, Fundamental Theory and Applications, pp. 1205-1211, November 1998.

M. A. Hasan, "Double-Basis Multiplicative Inversion in GF(2^m)," IEEE Trans. Computers, pp. 960-970, September 1998.

H. Wu and M. A. Hasan, "Low Complexity Bit-Parallel Multipliers for a Class of Finite Fields," IEEE Trans. Computers, pp. 883-887, August 1998.

M. A. Hasan, "Division-and-Accumulation over GF(2^m)," IEEE Trans. Computers, pp. 705-708, June 1997.

H. Wu and M. A. Hasan, "Efficient Exponentiation of a Primitive Root in GF(2^m)," IEEE Trans. Computers, pp. 162-172, Feb. 1997.

M. A. Hasan and V. K. Bhargava, "Architecture for a Low Complexity Rate-Adaptive Reed-Solomon Encoder," IEEE Trans. Computers, pp.938-942, July 1995.

M. A. Hasan, J. C. Lee and V. K. Bhargava, "A Narrowband Interference Canceller with an Adjustable Center Weight," IEEE Trans. Communications, pp. 877-880, Feb.-March 1994.

M. A. Hasan, M. Z. Wang and V. K. Bhargava, "A Modified Massey-Omura Parallel Multiplier for a Class of Finite Fields," IEEE Trans. Computers, pp.1278-1280, October 1993.

M. A. Hasan and V. K. Bhargava, "A Low Complexity Architecture for Exponentiation in GF(2^m)," IEE Electronics Letters, vol. 28, no. 21,  pp. 1984-1986, October 1992.

M. A. Hasan and V. K. Bhargava, "Bit-Serial Systolic Divider and Multiplier for Finite Fields GF(2^m)," IEEE Trans. Computers, pp. 972-980, August 1992.

M. A. Hasan, M. Z. Wang and V. K. Bhargava, "Modular Construction of Low Complexity Parallel Multipliers for a Class of Finite Fields GF(2^m)," IEEE Trans. Computers, pp. 962-971, August 1992.

M. A. Hasan and V. K. Bhargava, "Division and Bit-Serial Multiplication over GF(q^m)," IEE Proc. Computers and Digital Techniques, pp. 230-236, May 1992.